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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2012-03-07 10:45 |
Oita | B-con Plaza | Equivalence Checking Method of Timed Logic Formulae for Design Verification of Single-Flux Quantum Circuits Takahiro Kawaguchi (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)  VLD2011-135 |
This paper proposes an equivalence checking method of timed logic formulae for reducing number of states in verificatio... [more] |
VLD2011-135 pp.91-96 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2011-03-18 10:55 |
Okinawa | Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits Nobutaka Kito (Kyoto Univ.), Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2010-74 DC2010-73 |
Single Flux Quqntum(SFQ) logic circuits are expected to achieve ultra-high-performance computers with low power. For r... [more] |
CPSY2010-74 DC2010-73 pp.51-56 |
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| SCE | 2010-07-22 09:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High-Speed Operation of Single Flux Quantum Logic Up/Down Counter for Digital DROS Kosuke Terui, Yun Kimimoto, Tohru Taino, Hiroaki Myoren (Saitama Univ.) SCE2010-15 |
A double relaxation Oscillation SQUID (DROS) acts as a flux to voltage-pulse converter. Combining a flux-locked loop (FL... [more] | SCE2010-15 pp.7-11 |
| SCE | 2010-07-22 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Fault Modeling and Test Generation for Single Flux Quantum Logic Circuits Nobutaka Kito (Kyoto Univ.), Masamitsu Tanaka, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) SCE2010-19 |
This report discusses fault modeling and test generation for Single Flux Quqntum(SFQ) logic circuits. SFQ circuits ar... [more] |
SCE2010-19 pp.31-35 |
| SCE | 2010-07-22 13:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Demonstration of a 4x4 SFQ switch fabricated with the ISTEC 10-kA/cm2 Nb Advanced process 2 Masato Ito, Irina Kataeva, Masakazu Okada, Tomohito Kouketsu, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki (Nagoya Univ.) SCE2010-21 |
We have evaluated the performance of the 4×4 SFQ switch which was designed and fabricated using ISTEC Advanced process ... [more] | SCE2010-21 pp.41-46 |
| SCE | 2009-10-20 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Logic Design Verification Method for SFQ Circuits Considering Pipeline Processing Behavior Motoki Sato, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ) SCE2009-17 |
We propose a verification method of pipeline processing behavior of SFQ circuits. SFQ logic circuits work synchronously ... [more] | SCE2009-17 pp.1-6 |
| SCE | 2009-10-20 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Dynamically Reconfigurable Single Flux Quantum Logic Gates Yuki Yamanashi, Ichiro Okawa, Nobuyuki Yoshikawa (Yokohama Nat. Univ.) SCE2009-20 |
Novel reconfigurable superconductive single flux quantum logic gates, the function of which can be dynamically defined b... [more] | SCE2009-20 pp.19-23 |
| SCE | 2008-10-30 14:50 |
Ibaraki | AIST | Demonstration of a Single-Flux-Quantum Floating-Point Divider for the Reconfigurable Data-path Masamitsu Tanaka, Koji Obata, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2008-27 |
We report implementation and experimental results of a single-flux-quantum (SFQ) floating-point serial divider developed... [more] | SCE2008-27 pp.29-34 |
| SCE | 2008-10-30 15:55 |
Ibaraki | AIST | Automated Routing Method for Multi-Layer SFQ Circuits Shota Takeshima, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) SCE2008-29 |
Recently, a lot of researches on designing digital circuits using Single Flux Quantum (SFQ) logic circuits have been c... [more] |
SCE2008-29 pp.39-44 |
| SCE | 2007-01-26 11:20 |
Tokyo | SRL | Development of pipelined bit-serial single-flux-quantum microprocessors Masamitsu Tanaka (Nagoya Univ.), Yuki Yamanashi (Yokohama National Univ.), Naoki Irie (Nagoya Univ.), Heejoung Park (Yokohama National Univ.), Shingo Iwasaki (Nagoya Univ.), Kazuhiro Taketomi (Yokohama National Univ.), Akira Fujimaki (Nagoya Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Hirotaka Terai (NICT), Shinichi Yorozu (NEC) |
A pipelined single-flux-quantum microprocessor, called CORE1$\beta$ has been designed and its perfect operations have be... [more] | SCE2006-33 pp.19-24 |
| SCE | 2006-07-06 10:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | SQUIDs for multi-chip modules of quantum-bits Toshiyuki Miyazaki (JST), Shinichi Yorozu (NEC), Masaaki Maezawa (AIST), Mutsuo Hidaka (ISTEC), Jaw-Shen Tsai (NEC) |
Single-flux-quantum (SFQ) logic circuit operates below 1~K is a natural candidate for the interface between superconduct... [more] | SCE2006-15 pp.19-22 |
| CAS | 2006-01-13 14:20 |
Miyazaki | A Transduction-based Framework to Synthesize RSFQ Circuits Shigeru Yamashita (NAIST), Katsunori Tanaka (NEC), Hideyuki Takada (Kyoto Univ.), Koji Obata, Kazuyoshi Takagi (Nagoya Univ.) |
In this paper, we propose a new framework to synthesize rapid single flux quantum (RSFQ) logic circuits. In our framewor... [more] | CAS2005-94 pp.43-48 |
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| SCE | 2005-07-27 11:35 |
Aomori | Hirosaki Univ. | Automatic logic synthesis scheme and tool implementation for Single-Flux-Quantum circuits Yoshio Kameda, Shinichi Yorozu, Yoshihito Hashimoto (SRL) |
Single-flux-quantum (SFQ) logic circuits provide us a faster operation with low power consumption using Josephson juncti... [more] | SCE2005-17 pp.27-32 |
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