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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 13:25 |
Iwate | Hotel Ruiz | Load buffer with conversion capability from tiled data to raster data for motion search Takumi Inomata, Atsushi Tachino, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.)  VLD2012-52 SIP2012-74 ICD2012-69 IE2012-76 |
For smooth video encoding, it is essential to speed up the motion search, which consumes the most part of the processin... [more] | VLD2012-52 SIP2012-74 ICD2012-69 IE2012-76 pp.65-70 |
| CPSY | 2012-10-12 09:20 |
Hiroshima | Object Detection Based on Haar-like Features with Massive-Parallel Memory-Embedded SIMD Matrix Processor Mutsumi Omori, Tetsushi Koide, Hirokazu Hiramoto (Hiroshima Univ.) CPSY2012-32 |
We have developed Massive-Parallel Memory-Embedded SIMD (Single Instruction Multiple Data) Matrix Processor which can pr... [more] | CPSY2012-32 pp.7-12 |
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| RECONF | 2010-09-17 11:50 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Performance Evaluation of the SIMD/MIMD Dynamic Mode Switching Processor IMAPCAR2 Shorin Kyo, Shohei Nomoto, Shinichiro Okazaki (RE) RECONF2010-36 |
An image recognition ASSP (Application Specific Standard Product) is a kind of processor designed to be able to outper... [more] |
RECONF2010-36 pp.109-114 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
An Improved Face-Detection Method for a Massive-Parallel Memory-Embedded SIMD Matrix Processor MX-1 Hirokazu Hiramoto, Takeshi Kumaki, Yuta Imai, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.) ICD2009-92 |
Recently, face-detection processing is more widely used in security applications, such as video surveillance system or e... [more] | ICD2009-92 pp.83-88 |
| CAS, NLP | 2009-09-24 16:00 |
Hiroshima | Hiroshima Univ. Higashi Senda Campus | [Invited Talk]
Massive-Parallel Memory-Embedded SIMD Processor Architecture Tetsushi Koide, Takeshi Kumaki, Hans Juergen Mattausch (Hiroshima Univ.) CAS2009-34 NLP2009-70 |
A multimedia processor requires the four capabilities offast processing, small area size, low power consumption and pr... [more] |
CAS2009-34 NLP2009-70 pp.59-64 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | * Yuri Nishikawa (Keio Univ.), Michihiro Koibuchi (NII), Masato Yoshimi (Doshisha Univ.), Akihiro Shitara (Keio Univ.), Kenichi Miura (NII), Hideharu Amano (Keio Univ.) CPSY2009-25 |
ClearSpeed’s CSX600 that consists of 96 Processing Elements (PEs) employs a one-dimensional array topology for a simple ... [more] | CPSY2009-25 pp.91-96 |
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| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2009-03-06 13:30 |
Niigata | Sado Island Integrated Development Center | A implementation of RSA encryption using Interleaved Modular Multiplication for MX Core Wataru Kuroki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2008-102 DC2008-93 |
MX Core is a massively parallel SIMD（Single Instruction Multiple Data） type processor which have fine-grained computing ... [more] | CPSY2008-102 DC2008-93 pp.85-90 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 15:10 |
Kanagawa | Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-103 CPSY2008-65 RECONF2008-67 |
MX-Core is a massively parallel SIMD(Single Instruction Multiple Data) type processor which have ne-grained computing u... [more] | VLD2008-103 CPSY2008-65 RECONF2008-67 pp.69-74 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 17:25 |
Kanagawa | A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-108 CPSY2008-70 RECONF2008-72 |
Small area, high performance and high productivity are required for application-specific processors in embedded systems.... [more] | VLD2008-108 CPSY2008-70 RECONF2008-72 pp.99-104 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 13:25 |
Fukuoka | Kitakyushu Science and Research Park | An optimization method for MIMD controlled data communication of MX Core Akihiro Kodama, Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2008-42 |
The massively parallel SIMD (Single Instruction Multiple Data) processor MX Core, which has been developed by Renesas te... [more] | CPSY2008-42 pp.31-36 |
| CPSY | 2008-10-31 14:30 |
Hiroshima | Hiroshima City Univ. | Optimization method of data communication PEs for Massively Parallel SIMD processor Sumio Hirota, Akihiro Kodama, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2008-33 |
The MX core is a massively parallel SIMD (Single Instruction Multiple Data) processor based on fine-grained 1,024 PEs (P... [more] | CPSY2008-33 pp.23-28 |
| SIS | 2008-06-13 12:50 |
Hokkaido | Application of the massively parallel embedded processor (MX) to real-time image processing Hiroyuki Yamasaki, Takeaki Sugimura, Hideyuki Noda, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas) SIS2008-20 |
We developed the massively parallel embedded processor core (MX core) for the SoC(System on Chip) building in as an acce... [more] | SIS2008-20 pp.33-38 |
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| RECONF | 2008-05-22 15:15 |
Fukushima | The University of Aizu | Path Planning Method for MIMD Controlled data communication in MX Core Akihiro Kodama, Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (kumamoto Univ.) RECONF2008-6 |
The MX core is a massively parallel SIMD (Single Instruction Multiple Data) processor based on fine-grained 1,024 PEs (P... [more] | RECONF2008-6 pp.31-36 |
| RECONF | 2008-05-23 11:15 |
Fukushima | The University of Aizu | How fast is an FPGA in image processing ? Takashi Saegusa, Tsutomu Maruyama, Yoshiki Yamaguchi (Univ. of Tsukuba) RECONF2008-15 |
In image processing, FPGAs have shown very high performance in spite of their slow operational frequency. % The main ... [more] |
RECONF2008-15 pp.83-88 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 10:15 |
Kanagawa | Hiyoshi Campus, Keio University | Improvement in data communication between PEs for SIMD type processor MX core Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) VLD2007-121 CPSY2007-64 RECONF2007-67 |
We are researching about MX Core developed in Renesas Technology Corp.. MX Core is SIMD(Single Instruction Multiple Data... [more] | VLD2007-121 CPSY2007-64 RECONF2007-67 pp.19-24 |
| ICD, ITE-CE | 2007-12-14 14:40 |
Kochi | A multi matrix-processor core architecture for real-time image processing SoC Katsuya Mizumoto, Takayuki Gyohten, Tetsushi Tanizaki, Soichi Kobayashi, Masami Nakajima, Hiroyuki Yamasaki, Hideyuki Noda, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) ICD2007-138 |
This paper describes a real time image processing SoC(MX-SoC) with programmable multi matrix -processor(MX-Core) archite... [more] | ICD2007-138 pp.107-111 |
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| MI | 2007-11-16 09:25 |
Ishikawa | Kanazawa Univ. | SIMD-based computation of similarity measure and geometric transformation for fast image registration Yoshitaka Masutani, Shigeru Kiryuu, Shouhei Hanaoka, Yukihiro Nomura, Mitsutaka Nemoto, Naoto Hayashi, Shigeki Aoki, Kuni Ohtomo (UT) MI2007-49 |
Image registration is one of the key technologies in medical imaging, and requires high computational cost. We implemen... [more] | MI2007-49 pp.7-12 |
| CPSY | 2007-10-25 13:00 |
Kumamoto | Kumamoto University | The application of the massively parallel processor based on the matrix architecture Katsuya Mizumoto, Hiroyuki Yamasaki, Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Masami Nakajima, Motoki Higashida, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-24 |
We have developed programmable matrix-processor "MX-1". The MX-1 consists of MX-Core and a control CPU. The MX-Core is a... [more] | CPSY2007-24 pp.1-5 |
| CPSY | 2007-10-25 13:40 |
Kumamoto | Kumamoto University | The program development method of the massively parallel processor based on the matrix architecture. Hiroyuki Yamasaki, Katsuya Mizumoto, Hideyuki Noda, Tetsu Nishijima, Kanako Yoshida, Takeaki Sugimura, Takashi Kurafuji, Osamu Yamamoto, Yoshihiro Okuno, Kazutami Arimoto (Renesas) CPSY2007-25 |
Recently, the installed applications in the digital devices has been remarkably progressed. Considering these background... [more] | CPSY2007-25 pp.7-12 |
| CPSY | 2007-10-25 14:20 |
Kumamoto | Kumamoto University | An Implementation and evaluation of Ant Colony Optimization for massively parallel SIMD processor MX Core Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) CPSY2007-26 |
We focus on massively parallel processor based on the matrix architecture (MX Core) developed by Renesas Technology Cor... [more] |
CPSY2007-26 pp.13-18 |
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