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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| PN | 2024-04-30 16:05 |
Tokyo | (Primary: On-site, Secondary: Online) |
[Invited Talk]
8K ultra-high definition video handling system using a high bandwidth, low latency real-time processing platform Mitsuru Maruyama, Katsuhiro Sebayashi, Hajime Iwata (KAIT), Hiroyuki Kimiyama (Daido Univ.), Takayuki Nakachi (Ryukyus Univ.), Yasuhisa Kato (Miharu) |
(To be available after the conference date) [more] | |
| ITS, IE, ITE-MMS, ITE-ME, ITE-AIT [detail] | 2024-02-20 12:30 |
Hokkaido | Hokkaido Univ. | Lookup Table using SIMD register for Accelerating Variable-Weighted Convolution Yuki Naganawa, Hirokazu Kamei, Norishige Fukushima (NIT)  ITS2023-66 IE2023-55 |
(To be available after the conference date) [more] | ITS2023-66 IE2023-55 pp.106-111 |
| RECONF | 2023-08-04 15:35 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Improving Data Transfer Efficiency in Many-Core Systems with a RISC-V ISA Extension Masaru Nishimura, Yuxi Tan, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2023-16 |
The difficulty of balancing usability and efficient use of PEs and insufficient memory bandwidth are major issues for ma... [more] | RECONF2023-16 pp.13-18 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2023-03-23 16:25 |
Kagoshima | Amagi Town Disaster Prevention Center (Tokunoshima) (Primary: On-site, Secondary: Online) |
Evaluation of Bit-Reduced Homomorphic Encryption Library on Intel Xeon and Fujitsu A64FX Masaki Nishi, Teppei Shishido, Xinyi Li, Keiji Kimura (Waseda Univ.), Kentaro Sano (RIKEN) CPSY2022-38 DC2022-97 |
As deep learning is used in various applications, the protection of training data, input data, inference results, and tr... [more] | CPSY2022-38 DC2022-97 pp.25-30 |
| IA | 2022-10-14 15:55 |
Tokyo | Koshiba Hall, The University of Tokyo (Primary: On-site, Secondary: Online) |
8K ultra-high-definition video transcoding function using edge computing Yuma Ito (KAIT), Kouta Aoki (Miharu communications Inc.), Katsuhiro Sebayashi (KAIT), Hiroyuki Kimiyama (Daido University), Mitsuru Maruyama (KAIT) IA2022-35 |
The purpose of the research is to develop a practical technology for high-speed network computing including terminal, ed... [more] | IA2022-35 pp.15-20 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-28 15:45 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Acceleration of HE-Transformer with bit reduced SEAL and HEXL Xinyi Li, Masaki Nishi, Teppei Shishido, Keiji Kimura (Waseda Univ.) CPSY2022-12 DC2022-12 |
While cloud applications are covering people's privacy data, their related risks, such as theft risk, leak risk, and oth... [more] | CPSY2022-12 DC2022-12 pp.65-70 |
| IT, ISEC, RCC, WBS | 2022-03-11 14:05 |
Online | Online | Rocca: Efficient AES-based Encryption Scheme for Beyond 5G Kosei Sakamoto, Fukang Liu (Univ of Hyogo), Yuto Nakano, Shinsaku Kiyomoto (KDDI Research), Takanori Isobe (Univ of Hyogo/NICT) IT2021-126 ISEC2021-91 WBS2021-94 RCC2021-101 |
In this paper, we present an AES-based authenticated-encryption with associated-data scheme nemed Rocca, with the purpos... [more] | IT2021-126 ISEC2021-91 WBS2021-94 RCC2021-101 pp.249-255 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-11 10:30 |
Online | Online | Acceleration of Homomorphic Encryption Library SEAL by Reducing the Number of Arithmetic Bits Teppei Shishido, Masaki Nishi, Xinyi LI, Keiji Kimura (Waseda Univ.) CPSY2021-60 DC2021-94 |
(To be available after the conference date) [more] | CPSY2021-60 DC2021-94 pp.91-96 |
| RECONF | 2020-05-29 15:05 |
Online | Online | A tightly-connected RISC-V manycore processor in a SIMD manner Tan Yuxi, Riadh Ben Abdelhamid, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2020-17 |
The size and complexity of scientific and industrial applications have grown larger with computational technology develo... [more] | RECONF2020-17 pp.91-96 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2020-02-27 17:20 |
Kagoshima | Yoron-cho Chuou-Kouminkan | Toward acceleration of matrix multiplication on homomorphic encryption library Tetsuya Makita, Teppei Shishido (Waseda Univ.), Yasutaka Wada (Meisei Univ.), Keiji Kimura (Waseda Univ.) CPSY2019-96 DC2019-102 |
(To be available after the conference date) [more] | CPSY2019-96 DC2019-102 pp.51-56 |
| EMM, IT | 2019-05-23 15:55 |
Hokkaido | Asahikawa International Conference Hall | The Weight Distributions of the (256,k) Extended Binary Primitive BCH Codes with k=71, 187, 191, and 199 Toru Fujiwara (Osaka Univ.), Takuya Kusaka (Okayama Univ.) IT2019-5 EMM2019-5 |
Computing the weight distribution of a code when the formula for the distribution is unknown is a challenging problem in... [more] | IT2019-5 EMM2019-5 pp.23-28 |
| CPSY, DC, IPSJ-ARC [detail] | 2018-06-14 13:40 |
Yamagata | Takamiya Rurikura Resort | Optimized Pfaffian Computation Yudai Konno, Yoshihide Yoshimoto (UT) CPSY2018-1 DC2018-1 |
The Pfaffian is a homogeneous polynomial defined for a skew-symmetric matrix. The Pfaffian has similar characteristics ... [more] |
CPSY2018-1 DC2018-1 pp.19-23 |
| PRMU, IE, MI, SIP | 2017-05-25 13:00 |
Aichi | Image Rearrangement for Vectorized Operations in FIR Filtering Yoshihiro Maeda, Shota Yamashita, Masahiro Nakamura, Norishige Fukushima, Hiroshi Matsuo (NIT) SIP2017-3 IE2017-3 PRMU2017-3 MI2017-3 |
In this paper, we focus vectorized programming for revisited FIR image filtering. We propose a new design pattern of ve... [more] |
SIP2017-3 IE2017-3 PRMU2017-3 MI2017-3 pp.13-18 |
|
| IE, ITS, ITE-AIT, ITE-HI, ITE-ME, ITE-MMS, ITE-CE [detail] | 2017-02-21 11:30 |
Hokkaido | Hokkaido Univ. | Motion Estimation Algorithm for a SIMD Datapath adding Highly Efficient Local Search Function Yuuki Minoura, Toshio Kondo, Yuki Fukazawa, Takahiro Sasaki (Mie Univ.) ITS2016-50 IE2016-108 |
High efficiency video coding standard H.265 doubles the data compression ratio compared to H.264, however it is difficul... [more] | ITS2016-50 IE2016-108 pp.235-240 |
| IE | 2015-06-18 15:20 |
Okinawa | Okinawa Cellular | Highly efficient Motion Estimation Algorithmfrequently using SIMD Instructions for small search range Yuuki Minoura, Toshio Kondo, Yuki Fukazawa, Takahiro Sasaki (Mie Univ.) IE2015-38 |
High efficiency video coding standard H.265 was finalized in the recent progress of the high definition video technology... [more] | IE2015-38 pp.35-40 |
| ICD, CPSY | 2014-12-01 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Consideration of SIMD Acceleration for a MIPS Instruction Processor
-- A case study of processor design contest -- Kosuke Hiraishi, Akihiro Hashimoto, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota (Utsunomiya Univ.) ICD2014-73 CPSY2014-85 |
In the system development using soft core processor on an FPGA (Field Programmable Gate Array), an access to external me... [more] | ICD2014-73 CPSY2014-85 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-75 |
In recent years, high speed and high precision computing is increasingly needed. Hardware support for IEEE754 compliant... [more] |
CPSY2014-75 pp.19-23 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:40 |
Oita | B-ConPlaza | A complex multiplier using two floating-point fused multiply-add unit Yuhei Takata, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-76 |
Complex operations are used in scientific computing and signal processing. Floating-point complex multiplication is imp... [more] |
CPSY2014-76 pp.25-29 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-03 10:45 |
Miyagi | Highly Efficient SIMD Data Path for Motion Estimation Keita Watanabe, Yuki Minoura, Yuki Fukazawa, Toshio Kondo, Takahiro Sasaki (Mie Univ.) VLD2014-71 ICD2014-64 IE2014-50 |
Recently, in the need for video encoding of high definition increasing, although video coding standard H.265 with the co... [more] | VLD2014-71 ICD2014-64 IE2014-50 pp.63-68 |
|
| EST | 2013-05-10 15:50 |
Kanagawa | NTT Science and Core Technology Laboratory Group | Comparison of Fixed Point and Floating Point Calculations for parallel processing of FDTD method using FPGA Ryota Takasu, Tempei Hasegawa, Yoichi Tomioka (Tokyo Univ. of Agriculture and Tech.), Tsugumichi Shibata, Mamoru Nakanishi (NTT), Hitoshi Kitazawa (Tokyo Univ. of Agriculture and Tech.) EST2013-9 |
In this paper, we discuss the advantages and disadvantages of fixed point and floating point arithmetic calculations of ... [more] | EST2013-9 pp.45-50 |
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