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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | On low power oriented test pattern compaction using SAT solver Yusuke Matsunaga (Kyushu Univ.)  VLD2017-43 DC2017-49 |
This paper proposes a test pattern compaction method under power consumption constraint, which uses SAT solver based ... [more] |
VLD2017-43 DC2017-49 pp.95-99 |
| SIP, CAS, MSS, VLD | 2017-06-20 14:50 |
Niigata | Niigata University, Ikarashi Campus | SAT model sampling for test pattern generation considering signal transition activities Yusuke Matsunaga (Kyushu Univ.) CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21 |
This paper presents a test pattern generation method with considering signal transition activities using a SAT solver... [more] |
CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21 pp.107-112 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:50 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | On SAT based test pattern generation for transition faults considering signal activities Yusuke Matsunaga (Kyushu Univ.) VLD2016-63 DC2016-57 |
This paper presents a test pattern generation method with considering signal transition activities using a SAT solver... [more] |
VLD2016-63 DC2016-57 pp.111-115 |
| SS | 2016-03-10 10:50 |
Okinawa | An extension of SQL for specifying combinatorial optimization problems Yusaku Uchida, Masahiko Sakai, Naoki Nishida (Nagoya Univ.) SS2015-80 |
The performance of satisfiability (SAT) solvers have incredibly improved in recent years. It is, however, difficult to ... [more] |
SS2015-80 pp.25-30 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2015-51 DC2015-47 |
In layout design for LSI circuits, the layout area is minimized to reduce the fabrication cost and to increase the yield... [more] | VLD2015-51 DC2015-47 pp.81-86 |
| MSS, SS | 2015-01-27 09:20 |
Tottori | A supervisor synthesis by MaxSAT solvers under partial observation Tatsuki Hirota, Shoji Yuen (Nagoya Univ), Tetsuya Tohdo (DENSO) MSS2014-82 SS2014-46 |
Synthesis of the supervisor for discrete event systems under partial observation has been shown exponen- tial in princi... [more] |
MSS2014-82 SS2014-46 pp.79-84 |
|
| DC | 2014-10-27 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | SAT-based evaluation of cascading failures in inter-dependent networks Tatsuhiro Tsuchiya (Osaka Univ.) DC2014-21 |
We propose using a Boolean satisfiability (SAT) solver for an efficient analysis of cascading failures that can occur in... [more] | DC2014-21 pp.1-3 |
| SS | 2014-10-24 10:30 |
Kochi | Kochi city culture-plaza cul-port | Deriving supremal controllable sub-specifications in discrete event systems using MaxSAT solvers. Tatsuki Hirota, Shoji Yuen (Nagoya Univ), Tetsuya Tohdo (DENSO) SS2014-31 |
A discrete event system, DES for short, makes state transitions by discrete occurrences of events.System behavior is mod... [more] | SS2014-31 pp.35-40 |
| SS | 2014-03-11 10:30 |
Okinawa | Tenbusu Naha | Generation and Verification of Decision Table using SAT Solver Shinji Itoh, Naoto Sato, Hidetaka Kondoh, Kunihiko Miyazaki, Hiroki Mori, Makoto Kimura, Kiyoshi Yamaguchi (Hitachi) SS2013-73 |
Use of a decision table is an effective method to prevent defects of combination patterns of conditions. However, it is ... [more] | SS2013-73 pp.7-11 |
| SS, MSS | 2014-01-30 13:00 |
Aichi | Scheduling of Multi-Hop Control Networks with Optimal Control Performance Yasuki Nanamori, Toshimitsu Ushio (Osaka Univ.) MSS2013-51 SS2013-48 |
We propose a scheduling method to achieve the optimal control performance in a multi-hop control network, where actuatio... [more] | MSS2013-51 SS2013-48 pp.1-4 |
|
| COMP | 2013-03-18 14:35 |
Gifu | Gifu University | Comparative evaluation of two constructions of Hamiltonian circuits for generating picturesque mazes with illusory images Fuhito Yanagitani, Akihiro Uejima (Osaka Electro-Comm. Univ.) COMP2012-58 |
This report proposes a new type of maze generation as a generalization of the {\it picturesque maze generation problem},... [more] | COMP2012-58 pp.39-46 |
| DC | 2013-02-13 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Accelerating techniques for SAT-based test pattern generation Yusuke Matsunaga (Kyushu Univ.) DC2012-81 |
A naive way to solve ATPG problem using SAT solver is to formulate a test generation problem for a fault at a time. Thi... [more] |
DC2012-81 pp.7-12 |
| CAS | 2013-01-29 16:25 |
Oita | Beppu International Convention Center | SAT Solver based Motion Planning for Robots Takuya Suzuki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) CAS2012-91 |
As the scale of robot systems becoming larger, it will be difficult for the developer to manually program each motion, s... [more] | CAS2012-91 pp.137-141 |
| SS | 2013-01-10 15:15 |
Okinawa | Using SAT Solvers for Solving Control-Instruction Layout Problems in Low-Level Assembly Programming for Malbolge Satoshi Ando, Masahiko Sakai, Toshiki Sakabe, Keiichirou Kusakari, Naoki Nishida (Nagoya Univ.) |
Malbolge is known as one of the most esoteric programming languages. Although it became possible to write programs in M... [more] | SS2012-50 pp.25-30 |
|
| DC | 2012-12-14 17:00 |
Fukui | Aossa (Fukui) | Verification of Automatic Block System for Single Line Using SMT Solver Natsuki Terada (RTRI) DC2012-79 |
Formal methods are expected to increase reliability of software, including that of signaling systems. We modeled the sp... [more] | DC2012-79 pp.31-36 |
| SS, IPSJ-SE | 2012-11-01 10:25 |
Hiroshima | Hiroshima City University | A SAT Encoding for Finding Operation Sequences of Malbolge that Implement Trit-wise Functions Satoshi Ando, Masahiko Sakai, Toshiki Sakabe, Keiichirou Kusakari, Naoki Nishida (Nagoya Univ.) SS2012-37 |
Malbolge is known to be one of the most esoteric programming languages. Although it becomes possible to write programs i... [more] | SS2012-37 pp.7-12 |
| MSS, CAS | 2012-11-02 13:30 |
Iwate | Iwate University | Scheduling and Resource Assignment of Periodic Tasks in Computer Networks Using an SMT Solver Yuya Sakai, Toshimitsu Ushio (Osaka Univ.) CAS2012-62 MSS2012-42 |
It is important in computer networks to assign each task to a computer in order to have scheduling without deadline miss... [more] | CAS2012-62 MSS2012-42 pp.71-74 |
| VLD, CAS, MSS, SIP | 2012-07-03 15:50 |
Kyoto | Kyoto Research Park | Co-scheduling of Communication and Control of Multi-Hop Control Networks. Yasuki Nanamori, Toshimitsu Ushio (Osaka Univ.) CAS2012-27 VLD2012-37 SIP2012-59 MSS2012-27 |
We consider a multi-hop control network where a wireless network is used for transmission of input and output data betwe... [more] | CAS2012-27 VLD2012-37 SIP2012-59 MSS2012-27 pp.143-148 |
| SS | 2011-10-28 12:15 |
Ishikawa | JAIST | Incorporating Elementary Symmetric Clauses into SAT Solvers with Two-Watched-Literal Scheme Yoshizane Hino, Masahiko Sakai, Toshiki Sakabe, Keiichirou Kusakari, Naoki Nishida (Nagoya Univ.) SS2011-38 |
Umano et al.\ introduced elementary symmetric clauses (ES-clauses) into CNF formula in 2010 as a method for improving SA... [more] | SS2011-38 pp.67-72 |
| RECONF | 2011-09-27 14:10 |
Aichi | Nagoya Univ. | Variable and Clause Elimination in SAT problems using an FPGA Masayuki Suzuki, Tsutomu Maruyama (Univ. of Tsukuba) RECONF2011-40 |
The satisfiability (SAT) problem is to find an assignment of binary values to the variables which satisfy a given clausa... [more] | RECONF2011-40 pp.105-110 |
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