| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SIS, ITE-BCT | 2023-10-12 16:30 |
Yamaguchi | HISTORIA UBE (Primary: On-site, Secondary: Online) |
[Tutorial Lecture]
Technical Development of Intrusion Prevention Systems with Reconfigurable Devices Tomoaki Sato (Hokusei Gakuen Univ.)  SIS2023-19 |
The frequency of Internet use continues to increase in telework and remote work environments. Concurrently, there has be... [more] | SIS2023-19 pp.19-24 |
| PN | 2023-03-02 11:40 |
Okinawa | (Primary: On-site, Secondary: Online) |
Distributed DDoS Protection Method in the Core Network with Reconfigurable Device Edge Coordination Tomoki Naoi, Masaki Murakami, Yoshihiko Uematsu, Satoru Okamoto, Naoaki Yamanaka (Keidai) PN2022-58 |
Distributed Denial-of-Service (DDoS) attacks are a growing problem today, and it is difficult for individual users to mi... [more] | PN2022-58 pp.83-89 |
| CPSY, DC, IPSJ-ARC [detail] | 2022-07-28 13:30 |
Yamaguchi | Kaikyo Messe Shimonoseki (Primary: On-site, Secondary: Online) |
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Hideharu Amano (Keio Univ.), Masahiro Iida (Kumamoto Univ.) CPSY2022-8 DC2022-8 |
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] | CPSY2022-8 DC2022-8 pp.41-46 |
| PN | 2020-03-03 09:50 |
Kagoshima | (Cancelled but technical report was issued) |
DDoS defense method by logically isolating attackers Yutaka Nasu, Naoto Sumita, Masaki Murakami, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) PN2019-63 |
In recent years, the number of DDoS occurrences and the traffic volume have increased, and attacks have resulted in the ... [more] | PN2019-63 pp.65-71 |
| PN | 2019-11-14 17:20 |
Kanagawa | Network-based DDoS prevention with newly developed Reconfigurable Communication Processors Naoto Sumita, Masaki Murakami, Yu Nishio, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) PN2019-26 |
In order to cope with traffic growth and service diversity the Photonic Network Processor (PNP) has been proposed. As a ... [more] | PN2019-26 pp.15-22 |
|
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 10:25 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array Toru Katagiri, Hideharu Amano (Keio Univ.) VLD2013-122 CPSY2013-93 RECONF2013-76 |
Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high... [more] | VLD2013-122 CPSY2013-93 RECONF2013-76 pp.119-124 |
| RECONF | 2013-09-18 17:00 |
Ishikawa | Japan Advanced Institute of Science and Technology | A Restricted Dynamically Reconfigurable Architecture for Low Power Processors Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ.) RECONF2013-24 |
Reconfigurable processors have widely attracted attention as an approach to realize high-performance and highly energy-e... [more] | RECONF2013-24 pp.25-30 |
| RECONF | 2013-09-19 09:00 |
Ishikawa | Japan Advanced Institute of Science and Technology | A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.) RECONF2013-26 |
Leakage power is a serious problem especially for accerelators which use a large size Processing Ele- ment (PE) array. H... [more] | RECONF2013-26 pp.37-42 |
| IN | 2013-06-20 14:25 |
Fukui | University of Fukui, Bunkyo Campus, Memorial Academy Hall | Writing Window Join Processor in C Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) IN2013-26 |
In the past, there has always been a wide gap between the skills for designing software and hardware. Now that reconfigu... [more] | IN2013-26 pp.7-12 |
| RECONF | 2013-05-20 16:25 |
Kochi | Kochi Prefectural Culture Hall | Speed-up of Dynamically Reconfigurable Processor Array Toru Katagiri, Hideharu Amano (Keio Univ.) RECONF2013-5 |
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array (DRPA), it is common to increas... [more] | RECONF2013-5 pp.25-30 |
| RECONF | 2013-05-21 10:35 |
Kochi | Kochi Prefectural Culture Hall | Implementation of Speculative Gather System for CMA Rie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima, Hideharu Amano (Keio Univ.) RECONF2013-11 |
Cool Mega Array (CMA) is a low power reconfigurable processor array for battery driven mobile devices. A prototype chip ... [more] | RECONF2013-11 pp.55-60 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 17:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | [Keynote Address]
Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics) VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 |
DRP features two dimensional array of tiny processors and memories, onto which applications are compiled and mapped as a... [more] | VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 p.163(VLD), p.29(CPM), p.29(ICD), p.45(CPSY), p.163(DC), p.15(RECONF) |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 09:25 |
Iwate | Hotel Ruiz | Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size Yoshichika Fujioka (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.) VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71 pp.39-44 |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 13:00 |
Iwate | Hotel Ruiz | Accelerator Architecture for Multi Scale Filter Operation Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 |
Image recognition processing includes a number of filter operations which dominate the total execution time. Exploiting... [more] |
VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 pp.59-64 |
| RECONF | 2012-09-18 10:20 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | JPEG encoder design improvement and its evaluation for Dynamic Reconfigurable Circuit Hajime Sawano, Nobuyuki Araki, Takashi Kambe (Kinki Univ.) RECONF2012-26 |
Reconfigurable Computing (RC) has been proposed as a new paradigm to address the conflicting design requirements of high... [more] | RECONF2012-26 pp.13-18 |
| DC, CPSY (Joint) |
2012-08-02 16:15 |
Tottori | Torigin Bunka Kaikan | Co-processor of a low power accelerator CMA Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano (Keio Univ.) CPSY2012-14 |
Cool Mega-Array (CMA) is a novel high performance but low power reconfigurable accelerator consisting of a large PE(Proc... [more] | CPSY2012-14 pp.31-36 |
| RECONF | 2012-05-29 10:35 |
Okinawa | Tiruru (Naha Okinawa, Japan) | A study on memory controller of MuCCRA-3: Dynamically Reconfigurable Processor Array Toru Katagiri, Kazuei Hironaka, Hideharu Amano (Keio Univ.) RECONF2012-4 |
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array(DRPA), it is necessary to use P... [more] | RECONF2012-4 pp.19-24 |
| RECONF | 2012-05-29 11:25 |
Okinawa | Tiruru (Naha Okinawa, Japan) | Optimization of PE Array Interconnection on CMA to Reduce Configuration Data Rie Uno (keio Univ.), Nobuaki Ozaki, Hideharu Amano (Keio Univ.) RECONF2012-6 |
Cool Mega Array or CMA is a low power reconfigurable processor array for battery driven mobile devices.We developed a ... [more] |
RECONF2012-6 pp.31-36 |
| VLD | 2012-03-07 13:20 |
Oita | B-con Plaza | Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-138 |
This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s ... [more] | VLD2011-138 pp.109-114 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-25 16:20 |
Kanagawa | Hiyoshi Campus, Keio University | A Fast Approximate Solution of Energy Efficient Network Topology Using Reconfigurable Processor, STP Akiko Hirao, Hidetoshi Takeshita, Haruka Yonezu, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) VLD2011-102 CPSY2011-65 RECONF2011-61 |
Recently, the Internet is necessary tool for our daily lives, and the number of the Internet users is increasing particu... [more] | VLD2011-102 CPSY2011-65 RECONF2011-61 pp.67-72 |
[Return to Top Page]