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 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, VLD [detail] 2020-03-04
14:55		 Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)		 Gate Sizing for Programmable Delay Elements on Post-Silicon Delay Tuning
Kota Muroi, Yukihide Kohira (UoA) VLD2019-103 HWS2019-76		 Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] VLD2019-103 HWS2019-76
pp.53-58
VLD, HWS
(Joint)		 2018-03-01
09:50		 Okinawa Okinawa Seinen Kaikan Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning
Kota Muroi, Yukihide Kohira (Univ. of Aizu) VLD2017-107		 Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] VLD2017-107
pp.109-114
VLD 2017-03-01
14:50		 Okinawa Okinawa Seinen Kaikan Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-104		 Due to the progress of the process technology in LSI, the yield of chips is reduced by the timing violation because of t... [more] VLD2016-104
pp.13-18
CAS 2008-02-01
09:25		 Okinawa   A Post-Silicon Clock Tunig Method without Measuring the Variation Effects in Clock Signals
Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) CAS2007-95		 In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. Des... [more] CAS2007-95
pp.7-12
VLD, IPSJ-SLDM 2007-05-11
10:20		 Kyoto Kyodai Kaikan A Clock Deskew Method using PDE with Discrete Delay
Yuko Hashizume, Naoki Otani, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) VLD2007-9		 In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a c... [more] VLD2007-9
pp.13-18
ICD, VLD 2007-03-08
11:10		 Okinawa Mielparque Okinawa A Clock Deskew Method Using Statisical Presumption
Naoki Ootani, Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitayushu), Yuichi Nakamura (NEC) 		In deep-submicron technology, process variations can severely affect the performance and the yield of VLSI chips. As a c... [more] VLD2006-126 ICD2006-217
pp.43-48
 Results 1 - 6 of 6  /   
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