| IEICE Technical Committee Submission System Conference Schedule |
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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SS | 2024-03-08 09:55 |
Okinawa | (Primary: On-site, Secondary: Online) |
 SS2023-64 |
Dockerfile development projects usually support various base images, architectures, or versions of services. Depending o... [more] | SS2023-64 pp.91-96 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-15 14:40 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
A 183.4 nJ/inference 152.8 µW Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda (UTokyo) VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42 |
A 183.4-nJ/inference single-chip wired-logic DNN processor that is capable of recognizing all 35 commands defined in the... [more] | VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42 pp.54-59 |
| RECONF | 2023-08-04 15:35 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Improving Data Transfer Efficiency in Many-Core Systems with a RISC-V ISA Extension Masaru Nishimura, Yuxi Tan, Yoshiki Yamaguchi (Tsukuba Univ.) RECONF2023-16 |
The difficulty of balancing usability and efficient use of PEs and insufficient memory bandwidth are major issues for ma... [more] | RECONF2023-16 pp.13-18 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 14:50 |
Online | Online | Implementation of a RISC-V SMT Core in Virtual Engine Architecture Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65 |
The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] | VLD2021-57 CPSY2021-26 RECONF2021-65 pp.43-48 |
| HWS, VLD [detail] | 2021-03-04 09:30 |
Online | Online | Design space exploration on low energy embedded multi-core processors Sayuri Onagi, Yuko Hara (Tokyo Tech) VLD2020-79 HWS2020-54 |
Nowadays, edge computing has been sought by increasing stream data and demand for real time processing so that distribut... [more] | VLD2020-79 HWS2020-54 pp.61-66 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-23 13:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Design and implementation of a RISC-V computer system running Linux in Verilog HDL Junya Miura, Hiromu Miyazaki, Kenji Kise (Tokyo Tech) VLD2019-72 CPSY2019-70 RECONF2019-62 |
RISC-V is an instruction set architecture developed at the University of California, Berkeley. Processors using RISC-V ... [more] |
VLD2019-72 CPSY2019-70 RECONF2019-62 pp.117-122 |
| RECONF | 2019-05-09 12:35 |
Tokyo | Tokyo Tech Front | Efficient Instruction Fetch Architectures for a RISC-V Soft Processor Hiromu Miyazaki, Junya Miura, Kenji Kise (Tokyo Tech) RECONF2019-1 |
We aim to develop a cost-effective RISC-V scalar processor of pipelining for FPGAs. In this report, we try to implement ... [more] | RECONF2019-1 pp.1-6 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2018-07-30 14:30 |
Kumamoto | Kumamoto City International Center | Proposition and Implementation of RISC-V Processor with Data path extension for 10G Ethernet Yosuke Yanai, Takeshi Matsuya, Yohei Kuga, Tokusashi Yuta, Jun Murai (Keio Univ.) CPSY2018-15 |
In this paper, we propose a processor with 1024 bit wide data path for packet processing. A software packet processing e... [more] | CPSY2018-15 pp.33-38 |
| VLD, HWS (Joint) |
2018-02-28 15:25 |
Okinawa | Okinawa Seinen Kaikan | Architecture of Full-HD 60-fps Real-time Optical Flow Processor Satoshi Kanda (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) VLD2017-99 |
This paper describes the architecture design of Full-HD 60fps real-time optical flow processor. In this processor, the W... [more] | VLD2017-99 pp.61-66 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 12:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | CPSY2017-45 |
Generally, HDL simulation is used for development and verification of processor design. However, the simulation speed i... [more] |
CPSY2017-45 pp.53-58 |
| NS | 2017-10-26 14:55 |
Osaka | I-site nanba | [Poster Presentation]
Preliminary investigation of approximation analysis about low-latency network architecture Takeshi Kimura (Hokkaido Univ.), Krittin Intharawijitr (Tokyo Tech.), Katsuyoshi Iida, Yoshiaki Takai (Hokkaido Univ.) NS2017-104 |
In cloud computing, geographic distance between data centres and user devices may not let the delay requirement be satis... [more] | NS2017-104 pp.69-71 |
| ICD | 2017-04-21 09:35 |
Tokyo | [Invited Lecture]
Architectures and energy performance of nonvolatile SRAM for core-level nonvolatile power-gating Daiki Kitagata, Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara (Tokyo Inst. of Tech.) ICD2017-10 |
Architectures and energy performance of nonvolatile SRAM (NV-SRAM) are demonstrated for nonvolatile power-gating (NVPG) ... [more] | ICD2017-10 pp.51-56 |
|
| SIS | 2017-03-03 10:40 |
Kanagawa | Kanagawa Inst. Tech. Yokohama Office | A Study on Real-Time Property Using Multiprocessor SoC for Industrial Wireless LAN Systems Yushi Matsunaga, Mitsuru Hamada, Kyoshiro Sakamoto, Makoto Tsurita, Tatsumi Uwai, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi (Kyutech) SIS2016-57 |
Network (iWLAN) system to control industrial robots (iRBs)in factory automation (FA) environments is addressed. To impro... [more] | SIS2016-57 pp.87-90 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-24 17:20 |
Kanagawa | Hiyoshi Campus, Keio Univ. | A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption Kazumasa Ishikawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2016-92 CPSY2016-128 RECONF2016-73 |
In this paper, we presented a new residue addition algorithm using Signed-Digit (SD) numbers for the applications such a... [more] | VLD2016-92 CPSY2016-128 RECONF2016-73 pp.147-152 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Itaru Hida, Shinya Takamaeda, Masayuki Ikebe, Masato Motomura, Tetsuya Asai (Hokkaido Univ.) ICD2016-60 CPSY2016-66 |
In this paper, we propose a Bayesian branch prediction circuit consisting of an instruction-feature extractor and a naiv... [more] | ICD2016-60 CPSY2016-66 p.39 |
| ICD, CPSY | 2016-12-16 14:20 |
Tokyo | Tokyo Institute of Technology | [Invited Talk]
A Data-Driven Processor Realizing Trillion Sensors Universe Hiroaki Nishikawa (Univ. of Tsukuba) ICD2016-96 CPSY2016-102 |
This paper introduces a data-driven processor aiming at realizing Trillion Sensors Universe. Execution control scheme in... [more] | ICD2016-96 CPSY2016-102 pp.139-144 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | CSMA/CD and D-TDMA Hybrid Wireless 3D Bus Architecture Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) CPSY2015-69 |
(To be available after the conference date) [more] | CPSY2015-69 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Fast and Accurate Estimation of Execution Cycles for ARM Architecture Go Sato, Yuki Ando, Hiroaki Takada, Shinya Honda, Yutaka Matsubara (Nagoya Univ) VLD2015-73 DC2015-69 |
(To be available after the conference date) [more] | VLD2015-73 DC2015-69 pp.231-236 |
| R | 2015-10-16 11:00 |
Fukuoka | Irregularity Countermeasures in Massively Parallel BigData Processors Marat Zhanikeev (Kyutech) R2015-53 |
The term Massively Parallel BigData Processor names a recent advance in bigdata processing technology which has advanced... [more] | R2015-53 pp.7-14 |
|
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-04 10:00 |
Oita | B-Con Plaza (Beppu) | Design Space Exploration of Computational Photography Accelerator Yuttakon Yuttakonkit, Tran Thi Hong, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-17 |
Computational photography applications use image processing to extract quality improvement or addi- tional features. Ins... [more] | CPSY2015-17 pp.7-12 |
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