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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2021-02-05 10:30 |
Online | Online | A Study on a Method of Measuring Process Variations Considering the Effect of Wire Delay on FPGA Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.)  DC2020-69 |
FPGAs are integrated circuits that can be implemented arbitrary logic functions. In FPGAs, it is important to measure pr... [more] | DC2020-69 pp.1-6 |
| DC | 2021-02-05 10:55 |
Online | Online | Hardware Trojan Detection by Learning Power Side Channel Signals Considering Random Process Variation Michiko Inoue, Riaz-Ul-Haque Mian (NAIST) DC2020-70 |
Due to the globalization and complexity of the supply chain, there is a growing concern about the insertion of hardware ... [more] | DC2020-70 pp.7-11 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:10 |
Oita | B-ConPlaza | A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40 |
In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] | VLD2014-86 DC2014-40 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 16:00 |
Oita | B-ConPlaza | A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-103 DC2014-57 |
In this paper, we propose a high-level synthesis algorithm with delay variation tolerance optimization for RDR architect... [more] | VLD2014-103 DC2014-57 pp.209-214 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-08 09:00 |
Aomori | A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-54 ICD2013-78 IE2013-54 |
As device feature size drops, interconnection delays often exceed gate delays. We have to incorporate interconnection ... [more] |
VLD2013-54 ICD2013-78 IE2013-54 pp.41-46 |
|
| NS | 2012-05-18 11:15 |
Tokyo | National Institute of Informatics | A scheme for link-utilization estimation based on delay measurements considering of packet processing delay jitter and timer granularity Kiyofumi Igai, Eiji Oki (UEC) NS2012-28 |
This paper proposes a link utilization estimation scheme based on Round-Trip Time (RTT) measurement considering processi... [more] | NS2012-28 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:55 |
Miyazaki | NewWelCity Miyazaki | A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyu Univ) VLD2011-85 DC2011-61 |
It has the problem that good VLSIs in production testing become defective VLSIs in the fields because small delays on si... [more] | VLD2011-85 DC2011-61 pp.191-195 |
| DC | 2011-06-24 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyuushu Univ) DC2011-10 |
It has the problem that good VLSIs in production testing become defective VLSIs in the fields because small delays on si... [more] | DC2011-10 pp.11-16 |
| DC | 2011-02-14 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Analysis of Critical Paths for Field Testing with Process Variation Consideration Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushuu Univ) DC2010-61 |
Recently, it has the problem that good VLSIs in production testing become defective VLSIs in the fields because small de... [more] | DC2010-61 pp.13-19 |
| CS, IN, NS (Joint) |
2008-09-11 10:00 |
Miyagi | Tohoku University | Performance Evaluation of a Web-Server System with Proxy Cache Sites
-- Modeling and Analysis via Diffusion Process -- Yoshitaka Takahashi (Waseda Univ.), Yoshiaki Shikata (Shobi Univ.) IN2008-43 |
It is an important and urgent tele-traffic issue to evaluate and/or to estimate the delay in a web-server system handing... [more] | IN2008-43 pp.1-6 |
| DC, CPSY | 2008-04-23 11:00 |
Tokyo | Tokyo Univ. | A Lightweight Write Error Detection for Register-file Using Improved Passive WAB Hidetsugu Irie, Ken Sugimoto, Ryota Shioya (U-Tokyo), Kenichi Watanabe (Hitachi), Masahiro Goshima, Shuichi Sakai (U-Tokyo) CPSY2008-3 DC2008-3 |
Recently, it has been getting inefficient to design microprocessors with worst-case margins because of increasing proces... [more] | CPSY2008-3 DC2008-3 pp.13-18 |
| ICD, SDM | 2006-08-17 09:55 |
Hokkaido | Hokkaido University | A supply voltage adjustment technique for low power consumption and its application to SOCs with multiple threshold voltage CMOS Hiroshi Okano, Tetsuyoshi Shiota, Yukihito Kawabe (Fujitsu lab.), Wataru Shibamoto (Fujitsu), Tetsutaro Hashimoto, Atsuki Inoue (Fujitsu lab.) |
An energy-saving technique for SOCs using multiple threshold voltage CMOS was developed. It uses process sensors and pro... [more] | SDM2006-127 ICD2006-81 pp.13-18 |
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