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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 09:55 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Proposal of analytical expression for optimal store time of MTJ-based non-volatile flip-flops Daiki Yokoyama, Kimiyoshi Usami (SIT), Aika Kamei, Hideharu Amano (Keio Univ.)  VLD2022-39 ICD2022-56 DC2022-55 RECONF2022-62 |
LSI has been developed by miniaturization, but the increase in leakage power caused by it has become a problem. Non-vola... [more] | VLD2022-39 ICD2022-56 DC2022-55 RECONF2022-62 pp.115-120 |
| VLD, HWS [detail] | 2022-03-07 14:30 |
Online | Online | MTJ-based non-volatile SRAM circuit with Approximate Image-data Storing for energy saving Hisato Miyauchi, Kimiyoshi Usami (SIT) VLD2021-86 HWS2021-63 |
Non-volatile memory (NVM) using magnetic tunnel junction (MTJ) devices can prevent the increase in leakage current, whic... [more] | VLD2021-86 HWS2021-63 pp.51-56 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:10 |
Online | Online | MTJ-based non-volatile SRAM circuit with data-aware store control for energy saving Hisato Miyauchi, Kimiyoshi Usami (SIT) VLD2021-19 ICD2021-29 DC2021-25 RECONF2021-27 |
In recent years, the increase of leakage power in LSIs has become a problem, and one of the methods to reduce the leakag... [more] | VLD2021-19 ICD2021-29 DC2021-25 RECONF2021-27 pp.13-18 |
| HWS, VLD [detail] | 2020-03-04 13:00 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
MTJ-based Nonvolatile Flip-Flop Circuit Using Dual Power Supplies for Low-voltage Operation Sosuke Akiba, Kimiyoshi Usami (SIT) VLD2019-99 HWS2019-72 |
One of the leakage reduction techniques is nonvolatile power gating(NVPG) by using magnetic tunnel junction(MTJ). In the... [more] | VLD2019-99 HWS2019-72 pp.31-36 |
| VLD, IPSJ-SLDM | 2018-05-16 15:00 |
Fukuoka | Kitakyushu International Conference Center | Non-volatile Power Gating for Data Cache with Dynamic Line-selection Sosuke Akiba, Kimiyoshi Usami (SIT) VLD2018-2 |
In the whole of CPU, the proportion of energy consumption of the cache is increasing. Non-volatile Power Gating(NVPG) is... [more] | VLD2018-2 pp.19-24 |
| VLD, HWS (Joint) |
2018-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122 |
As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that ena... [more] | VLD2017-122 pp.199-204 |
| ICD | 2017-04-21 09:35 |
Tokyo | [Invited Lecture]
Architectures and energy performance of nonvolatile SRAM for core-level nonvolatile power-gating Daiki Kitagata, Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara (Tokyo Inst. of Tech.) ICD2017-10 |
Architectures and energy performance of nonvolatile SRAM (NV-SRAM) are demonstrated for nonvolatile power-gating (NVPG) ... [more] | ICD2017-10 pp.51-56 |
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| VLD | 2017-03-01 14:00 |
Okinawa | Okinawa Seinen Kaikan | Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines Shota Enokido, Kimiyoshi Usami (SIT) VLD2016-102 |
Non-volatile Power Gating(NVPG) is a technique to power gate memory elements to reduce leakage power while keeping the s... [more] | VLD2016-102 pp.1-6 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 10:15 |
Kanagawa | Hiyoshi Campus, Keio Univ. | MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami (SIT) VLD2016-97 CPSY2016-133 RECONF2016-78 |
With the spread of portable devices in recent year, products with high performance and low power consumption are require... [more] | VLD2016-97 CPSY2016-133 RECONF2016-78 pp.175-180 |
| VLD, CAS, MSS, SIP | 2016-06-17 09:50 |
Aomori | Hirosaki Shiritsu Kanko-kan | Design and Evaluation of MTJ-based Standard Cell Memory Junya Akaike, Masaru Kudo, Kimiyoshi Usami (SIT) CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 |
With the spread of portable devices, products with high performance and long battery life are required. In this paper, w... [more] | CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 pp.103-108 |
| ICD | 2014-04-18 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop Hiroki Koike (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Sadahiko Miura, Hiroaki Honjo, Tadahiko Sugibayashi (NEC), Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-17 |
We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel jun... [more] | ICD2014-17 pp.85-90 |
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