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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RCS, NS, USN (Joint) |
2012-07-20 16:15 |
Iwate | Iwate Univ. | Effect of k-th order PSD on timing jitter Daisuke Abe, Isamu Wakabayashi, Masatoshi Sano (TUS)  RCS2012-94 |
We have discussed the effect of kth order PSDs at the squarer output on timing jitter. Transmission schemes are assumed ... [more] | RCS2012-94 pp.115-119 |
| EMCJ, ITE-BCT | 2012-03-16 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Phase Comparator Sesitivity for Low Phase-Noise PLL Hideyasu Hobara, Yoshiki Kayano, Hiroshi Inoue (Akita Univ.) EMCJ2011-141 |
An UWB RF system can be used in the area of signal processing. The phase-noise of output voltage of the oscillator with ... [more] | EMCJ2011-141 pp.67-72 |
| CAS, CS, SIP | 2012-03-08 14:10 |
Niigata | The University of Niigata | A Low-Jitter 1.5-GHz and Large-EMI reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA Takashi Kawamoto (Hitachi), Masato Suzuki (Renesas) CAS2011-129 SIP2011-149 CS2011-121 |
A low-jitter and large-EMI-reduction spread spectrum clock generator (SSCG) for Serial-ATA (SATA) was developed. A low-j... [more] | CAS2011-129 SIP2011-149 CS2011-121 pp.125-130 |
| MW | 2012-03-02 10:00 |
Saga | Saga University | A Sub-harmonic Injection-locked Oscillator with Multiple Pulse Injection Koji Tsutsumi, Masaomi Tsuru, Eiji Taniguchi (Mitsubishi Electric) MW2011-180 |
A locking range of sub-harmonic injection-locked oscillator is inversely proportional to the frequency ratio between inj... [more] | MW2011-180 pp.71-75 |
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
Simulation and Analysis of the Interference Noise between PLL circuits. Ken Maruhashi, Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (Osaka Inst. Tech.), Yoshio Matsuda (Kanazawa Univ.) ICD2011-110 |
When the multiple PLL circuits are laid out on a single IC chip, the influence of the interference between PLL circuits ... [more] | ICD2011-110 pp.57-58 |
|
| CAS, NLP | 2011-10-21 15:05 |
Shizuoka | Shizuoka Univ. | White Noise Generation via Chaos from Phase-Locked Loops
-- Simulation Study by LTspice -- Yuhei Chiba, Kyosuke Kato, Isao Imai, Tetsuro Endo (Meiji Univ.) CAS2011-57 NLP2011-84 |
Phase-locked loops(PLLs) can generate chaos in some operating condition. In particular, the phase unbounded chaotic attr... [more] | CAS2011-57 NLP2011-84 pp.141-146 |
| OPE, MW, MWP, EMT, EST, IEE-EMT [detail] | 2011-07-22 14:50 |
Hokkaido | Phase-synchronous Chain of Two Multi-Carrier Lights Spaced at 25GHz by Cancelling Micro-wave Phase Noise Akira Mizutori, Atsushi Kodama, Masafumi Koga (Oita Univ.) MW2011-64 OPE2011-51 EST2011-50 MWP2011-32 |
This paper proposes and demonstrates a phase-synchronous chain technique for two phase-locked multi-carrier lights space... [more] | MW2011-64 OPE2011-51 EST2011-50 MWP2011-32 pp.145-149 |
|
| AP, SAT (Joint) |
2011-07-15 10:25 |
Nagano | Fac. Eng., Shinshu Univ. | Developemnt of bread board model for next generation optical inter-satellite communication
-- Verification of communication link between two terminals -- Toshiyuki Ando, Jiro Suzuki, Kazuhide Kodeki, Eisuke Haraguchi, Shigetaka Itakura, Yoshihito Hirano (Melco), Tatsuyuki Hanada, Shiro Yamakawa (JAXA) SAT2011-15 |
We have been developing next generation optical inter-satellite communication terminals based on coherent homodyne BPSK ... [more] | SAT2011-15 pp.43-48 |
| AP, MW (Joint) |
2011-03-03 15:20 |
Ibaraki | Ibaraki Univ. | A Low Noise Ku-band PLL using Parallel PFD with Multiple Timing Operation and Auto Delay Control Circuit of Reference Signal Koji Tsutsumi, Yoshinori Takahashi, Masahiko Komaki, Mitsuhiro Shimozawa (Mitsubishi Electric) MW2010-162 |
A Parallel PFD configuration is effective for reducing the PLL phase noise. However, the phase noise reduction will degr... [more] | MW2010-162 pp.57-61 |
| SIP, RCS | 2011-01-20 11:45 |
Kagoshima | The effect of a prefilter on timing jitter Isamu Wakabayashi, Shun-ichi Urano, Masatoshi Sano (TUS) SIP2010-78 RCS2010-208 |
Timing jitter in digital transmission systems has three components of SS, SN, and NN. The timing circuit is assumed to c... [more] | SIP2010-78 RCS2010-208 pp.55-60 |
|
| ICD | 2010-12-16 15:10 |
Tokyo | RCAST, Univ. of Tokyo | [Poster Presentation]
CMOS-Based Nonvolatile Flip-Flop Design and its Application to a Fractional-N PLL Frequency Synthesizer Ge Wang, Jungyu Lee, Shoichi Masui (Tohoku Univ.) ICD2010-100 |
A CMOS-based nonvolatile flip-flop (NV-FF) is proposed and implemented with a 180nm technology without any additional ma... [more] | ICD2010-100 pp.31-36 |
| ICD | 2010-12-16 15:10 |
Tokyo | RCAST, Univ. of Tokyo | [Poster Presentation]
A 0.5V 6-bit Scalable Phase Interpolator Satoshi Kumaki, Abul Hasan Johari, Takeshi Matsubara (Keio Univ), Isamu Hayashi (STARC), Hiroki Ishikuro (Keio Univ) ICD2010-110 |
This paper proposes a scalable phase interpolator (PI) with dual-input inverter. A pipelined architecture is proposed to... [more] | ICD2010-110 p.81 |
| SS | 2010-10-15 11:00 |
Iwate | Iwate Prefectural Univ. | On DPLL Transition Systems Modulo Equational Theories Tatsuya Baba, Toshiki Sakabe, Naoki Nishida, Keiichirou Kusakari, Masahiko Sakai (Nagoya Univ.) SS2010-36 |
SMT solvers are tools for deciding satisfiability of formulas under given theories such as arrays, lists, queues and so ... [more] | SS2010-36 pp.49-54 |
| ICD, ITE-IST | 2010-07-22 15:50 |
Osaka | Josho Gakuen Osaka Center | [Invited Talk]
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter Tadashi Maeda, Takashi Tokairin (Renesas Electronics Corporation), Masaki Kitsunezuka (NEC Corp.), Mitsuji Okada (Renesas Electronics Corporation), Muneo Fukaishi (NEC Corp.) ICD2010-29 |
A 2.1-to-2.8-GHz low-power consumption all-digital phase locked loop (ADPLL) with a time-windowed time-to-digital conver... [more] | ICD2010-29 pp.49-54 |
| ICD, ITE-IST | 2010-07-23 16:35 |
Osaka | Josho Gakuen Osaka Center | Self-Dithered Digital Delta Sigma Modulators for Fractional-N Frequency Synthesizers Zule Xu, Jun Gyu Lee, Shoichi Masui (Tohoku Univ.) ICD2010-36 |
Digital delta-sigma modulators applied in fractional-N frequency synthesizers suffer from spurious tones which undermine... [more] | ICD2010-36 pp.121-126 |
| SCE, MW | 2010-04-23 17:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Fast-acquisition PLL Using Fully Higital Natural-frequency-switching Technique Mitsuo Nakamura, Akihiro Yamagishi, Mitsuru Harada, Makoto Nakamura (NTT) SCE2010-13 MW2010-13 |
A new PLL with a simple architecture that overcomes the trade-off between the acquisition time and phase noise was in a ... [more] | SCE2010-13 MW2010-13 pp.69-73 |
| ICD | 2010-04-23 11:25 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
High-Speed Memory Interfaces
-- DDR/GDDR-DRAM -- Yasuhiro Takai (Elpida) ICD2010-15 |
(To be available after the conference date) [more] | ICD2010-15 pp.81-82 |
| MW | 2010-03-05 15:50 |
Kyoto | Ryukoku Univ. | A PLL Synthesizer Composed of Parallel Dual Modulus Prescaler with a step size of 0.5 Hideyuki Nakamizo, Kenichi Tajima, Ryoji Hayashi (Mitsubishi Electric Corp.), Toshiya Uozumi (Renesas Technology Corp.) MW2009-209 |
By reducing the step size of the programmable frequency divider in Fractional-N PLL from 1 to 0.5, the phase noise contr... [more] | MW2009-209 pp.175-178 |
| MW | 2010-03-05 16:15 |
Kyoto | Ryukoku Univ. | A Low Noise Ku-band PLL-IC using Parallel PFD with Multiple Timing Operation Koji Tsutsumi, Yoshinori Takahashi, Mitsuhiro Shimozawa, Masahiko Komaki, Noriharu Suematsu (Mitsubishi Electric Corp.) MW2009-210 |
A Parallel PFD configuration is effective for reducing the PLL phase noise. However, the phase noise reduction will degr... [more] | MW2009-210 pp.179-182 |
| CPSY | 2009-11-20 14:10 |
Kyoto | Campus Plaza Kyoto | Analyzing performance of storage access optimization with virtual machine migration Shiori Toyoshima (Ochanomizu Univ.), Saneyasu Yamaguchi (Kogakuin Univ.), Masato Oguchi (Ochanomizu Univ.) CPSY2009-37 |
We have constructed a virtual machine PC cluster that uses a virtual machine as worker nodes, and proposed a method that... [more] | CPSY2009-37 pp.13-18 |
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