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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, CPSY | 2015-12-18 16:45 |
Kyoto | Kyoto Institute of Technology | Autonomously Tracking PVT Variations of Pulse Width Controlled PLL using Hill-Climbing Method Toi Takashi, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada (Tokyo Univ.)  ICD2015-95 CPSY2015-108 |
[more] | ICD2015-95 CPSY2015-108 pp.135-140 |
| EMCJ, IEE-EMC, IEE-MAG | 2015-06-25 10:10 |
Overseas | KMITL, Thailand | EMI Reduction by Extended Spread Spectrum in Switching Converter Yasunori Kobori (NIT, Oyama College/Gunma Univ.), Nobukazu Tsukiji, Nobukazu Takai, Haruo Kobayashi (Gunma Univ.) EMCJ2015-18 |
This paper proposes new EMI reduction method by extended spread spectrum using the PLL circuit with pseudo analog noise ... [more] | EMCJ2015-18 pp.1-6 |
| MW, ICD | 2015-03-05 16:10 |
Fukui | University of Fukui | [Special Talk]
Ultra-Low Phase Noise Frequency Synthesizer for up to 28Gbps 60GHz Wireless Transceivers Ahmed Musa (NTT), Kenichi Okada, Akira Matsuzawa (Titech) MW2014-214 ICD2014-127 |
Phase noise of the synthesizer used in transceivers has a significant impact on the achievable performance. At 60GHz, ph... [more] | MW2014-214 ICD2014-127 pp.67-72 |
| MW, ICD | 2015-03-06 14:30 |
Fukui | University of Fukui | Basic characteristics of the third order PLL oscillator Junki Ogawa, Kenji Itoh, Keisuke Noguchi, Tetsuo Hirota, Shigeru Makino (KIT) MW2014-224 ICD2014-137 |
In this report, basic characteristics of the third order PLL oscillator are discussed with comparison of the second orde... [more] | MW2014-224 ICD2014-137 pp.123-126 |
| VLD | 2015-03-04 09:15 |
Okinawa | Okinawa Seinen Kaikan | On PLL Layouts Evaluation based on Transistor-array Style Yuki Miura, Atsushi Nanri, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2014-175 |
The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that uni... [more] | VLD2014-175 pp.123-128 |
| NC | 2015-01-30 10:25 |
Fukuoka | Kyushu Institute of Technology | Winner-Take-All neural network with DPLL considering scalability Masaki Azuma, Hiroomi Hikawa (Kansai Univ.) NC2014-65 |
This paper proposes a hardware winner-take-all neural network (WTANN) that employs a new winner-take-all (WTA) circuit w... [more] | NC2014-65 pp.47-52 |
| MW (2nd) |
2014-11-26 - 2014-11-28 |
Overseas | King Mongkut's Institute of Technology Ladkrabang (KMITL), Bangkok | A 0.5-V 5.8-GHz Current-Reuse-VCO-Based PLL with Amplitude Regulation Technique Sho Ikeda, Sang_yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Tech.) |
This paper presents design and detail measurement results of the ultra-low-power 5.8-GHz PLL with a current-reuse VCO an... [more] | |
| MW | 2014-11-21 15:20 |
Nagasaki | Nagasaki Univ. | A Spurious Suppression Method with DDS driven Fractional-N PLL Kazuhide Higuchi, Hiroyuki Mizutani, Kenichi Tajima, Morishige Hieda (Mitubishi Electric) MW2014-145 |
A Fractional-N PLL can generate high resolution frequency signals with the combination of  modulator and... [more] | MW2014-145 pp.119-122 |
| PN, NS, OCS (Joint) |
2014-06-26 10:50 |
Oita | B-ConPlaza | Costas Loop Homodyne detection for 20Gbit/s QPSK signal transmission Yusuke Shigeta, Akira Mizutori, Masafumi Koga (Oita Univ.) OCS2014-12 |
The optical fiber transmission experiment confirmed a stable Costas-Loop homodyne detection for 20Gbit/s QPSK signal. Su... [more] | OCS2014-12 pp.1-4 |
| MW | 2014-03-05 16:15 |
Ehime | Ehime University | Novel phase difference control technique of fractional-N PLL by using clock-shift of LE signal Yusuke Kitsukawa, Hideyuki Nakamizo, Kazunari Kihira, Kenichi Tajima, Kenji Kawakami (Mitsubishi Electric) MW2013-223 |
A novel phase control technique of microwave signals using a Fractional-N PLL(F-PLL) synthesizer is described. In multip... [more] | MW2013-223 pp.151-154 |
| VLD | 2014-03-05 10:50 |
Okinawa | Okinawa Seinen Kaikan | Analysis of Radiation-Induced Errors in PLL based on Behavioral Modeling SinNyoung Kim (Kyoto Univ.), Tomohiro Fujita (Ritsumeikan Univ.), Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) VLD2013-158 |
This paper presents an analysis of radiation-induced errors in PLL based on behavioral modeling. Radiation strike leads ... [more] | VLD2013-158 pp.131-136 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
An ultra-low-voltage power-supply monitor circuit for wireless-powered microparticle manipulation system Ji Cui, Hirosuke Iwasaki, Yoshiaki Dei, Toshimasa Matsuoka (Osaka Univ.) ICD2013-105 |
This paper presents a voltage sensor (VS) circuit to monitor the supply voltage induced on wireless-pow-ered micropartic... [more] | ICD2013-105 pp.15-18 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
A Design of 0.5V Subthreshold Digital Phase Locked Loop using Simple Synchronization Unit. Kousuke Watanabe, Tomochika Harada (Yamagata Univ.) ICD2013-129 |
In this paper, we design and evaluate the 0.5V subthreshold DPLL circuit. Under synchronization, fine tuning operation i... [more] | ICD2013-129 pp.67-72 |
| DC | 2013-12-13 13:25 |
Ishikawa | Variable Test-Timing Generation for Built-In Self-Test on FPGA Yasuo Sato, Munehiro Matsuura, Hitoshi Arakawa, Yousuke Miyake, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-69 |
This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Applica... [more] | DC2013-69 pp.7-12 |
|
| SAT | 2013-10-25 10:30 |
Fukuoka | IP CITY HOTEL Fukuoka | Synchronization Methods for Satellite Communications
-- for stability of the systems -- Osamu Ichiyoshi (HNfB21C) SAT2013-43 |
Phase Lock Loop(PLL) is widely used in communication systems. A big problem of the PLL is the limited pull in range, esp... [more] | SAT2013-43 pp.107-112 |
| EMCJ | 2013-04-12 11:55 |
Okayama | Okayama Univ. | Low Power CSSAL Bit-Parallel Multiplier over GF(2^4) in 0.18 um CMOS Technology Cancio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ.) EMCJ2013-3 |
本論文は，我々が提案したセキュア断熱的差動論理論理回路CSSALを用いて，ガロア体GF(2^4)を並列乗算器にて構成し，従来の2N-2N2P断熱論理とTDPLのそれらをポストレイアウトシミュレーションにて比較した結果を示す．Cadence ... [more] | EMCJ2013-3 pp.13-18 |
| ICD | 2012-12-17 15:55 |
Tokyo | Tokyo Tech Front | [Poster Presentation]
A New Approach of the Analysis of the ISF in Oscillators with a Closed-Loop Control Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2012-97 |
The derivation of the impulse sensitivity function (ISF) of oscillators are widely used for the evaluation of the phase ... [more] | ICD2012-97 pp.37-40 |
| ICD | 2012-12-17 15:55 |
Tokyo | Tokyo Tech Front | [Poster Presentation]
Analysis of the Pull-in Range in a CDR-PLL with the Nonlinearity of the Phase Detector Shinji Shimizu, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2012-100 |
The analysis of the lock-in process of CDR-PLLs using the nonlinear model of the phase detector is presented. The analys... [more] | ICD2012-100 pp.45-48 |
| MW | 2012-12-13 15:15 |
Yamanashi | Univ. of Yamanashi | Spurious level reduction method for FMCW signal source using PLL Hideyuki Nakamizo, Kenichi Tajima, Kenji Kawakami (Mitsubishi Electric Corp.) MW2012-130 |
(To be available after the conference date) [more] | MW2012-130 pp.19-23 |
| OFT, OCS, ITE-BCT, IEE-CMN (Joint) [detail] |
2012-11-21 13:25 |
Kumamoto | Costas loop base homodyne detection for 12.5-Gbit/s BPSK signal and its evolution to optical frequency synchronous photonic network Akira Mizutori, Masamichi Sugamoto (Oita Univ.), Atsushi Takada (TokushimaUniv.), Masafumi Koga (Oita Univ.) OCS2012-77 |
This paper demonstrates 12.5-Gbit/s BPSK decision-directed homodyne detection. The lag-lead loop filter with integrator ... [more] | OCS2012-77 pp.7-10 |
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