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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2024-04-11 13:50 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A 22 nm 10.8 Mb Embedded STT MRAM Macro Achieving over 200 MHz Random Read Access and a 10.4 MB/s Write Throughput for High End MCUs Masayuki Izuna, Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono (Renesas Electronics)  ICD2024-6 |
(To be available after the conference date) [more] | ICD2024-6 pp.18-19 |
| ICD | 2023-04-10 11:00 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono (Renesas Electronics) ICD2023-2 |
This paper presents a high-precision sense amplifier and a fast write throughput technique of a 32Mb embedded STT-MRAM m... [more] | ICD2023-2 p.7 |
| ICSS | 2020-11-26 16:00 |
Online | Online | Non-interactive oblivious transfer protocol based on TEE Masahide Kobayashi, Takashi Nishide (Univ. of Tsukuba) ICSS2020-24 |
Oblivious transfer is a protocol consisting of two parties, a data sender and receiver, and is used for secure computati... [more] | ICSS2020-24 pp.26-31 |
| IT, ISEC, WBS | 2019-03-08 13:30 |
Tokyo | University of Electro-Communications | One-Time Program and Its Application to Schnorr Signature Takashi Nishide (Univ. of Tsukuba) IT2018-108 ISEC2018-114 WBS2018-109 |
One-time programs (OTPs) are programs that can be executed only once. Goldwasser et al. constructed OTPs by relying on ... [more] |
IT2018-108 ISEC2018-114 WBS2018-109 pp.201-208 |
| SDM, ICD, ITE-IST [detail] | 2017-08-01 09:45 |
Hokkaido | Hokkaido-Univ. Multimedia Education Bldg. | Parallel Programming of Non-volatile Power-up States of SRAM Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya (Univ. of Tokyo), Hirofumi Shinohara (Waseda Univ.), Masaharu Kobayashi, Toshiro Hiramoto (Univ. of Tokyo) SDM2017-38 ICD2017-26 |
A technique for using an ordinary SRAM array for programmable and readable non-volatile (NV) memory is proposed. Paralle... [more] | SDM2017-38 ICD2017-26 pp.49-54 |
| ICD | 2008-04-18 10:00 |
Tokyo | A 65nm Pure CMOS One-time Programmable Memory Using a Two-Port Antifuse Cell Implemented in a Matrix Structure Kensuke Matsufuji, Toshimasa Namekawa, Hiroaki Nakano, Hiroshi Ito, Osamu Wada, Nobuaki Otsuka (Toshiba) ICD2008-8 |
A Pure CMOS One-time Programmable（PCOP）memory using an antifuse is presented. PCOP memory adopts two-port cell architect... [more] | ICD2008-8 pp.39-44 |
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