| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Error Pattern Analysis among Scaled Generations of NAND Flash Memories Yukiya Sakaki, Yusuke Yamaga, Ken Takeuchi (Chuo Univ.)  ICD2016-69 CPSY2016-75 |
The capacity of NAND flash memory can be expanded by memory cell scaling. However, bit-errors are increased by memory ce... [more] | ICD2016-69 CPSY2016-75 p.57 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Error Analysis of NAND Flash Memories for Long-Term Storage Kyoji Mizoguchi, Tomonori Takahashi, Seiichi Aritome, Ken Takeuchi (Chuo Univ.) ICD2016-72 CPSY2016-78 |
Recently, a digital data on art, culture and history which required data-retention (DR) time from 10 to 100 years or mor... [more] | ICD2016-72 CPSY2016-78 p.63 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
A Highly Reliable Method with Data-Retenrion Characteristics in TLC NAND Flash Memories Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi (Chuo Univ.) ICD2016-73 CPSY2016-79 |
The capacity of NAND flash memory can be expanded by multi-level cell technology. In particular, 3-bit/cell triple-level... [more] | ICD2016-73 CPSY2016-79 p.65 |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Reduction of Data-Retention Error in TLC NAND Flash Memories Yuichi Sato, Yoshiaki Deguchi, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2016-76 CPSY2016-82 |
The cost of NAND flash memory is reduced by scaling and multi-level cell technologies. However, the reliability of tripl... [more] | ICD2016-76 CPSY2016-82 p.75 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Optimal configuration design of SCM and MLC/TLC NAND flash memory in semiconductor storage system Chihiro Matsui, Yusuke Yamaga, Yusuke Sugiyama, Ken Takeuchi (Chuo Univ.) CPM2016-77 ICD2016-38 IE2016-72 |
In order to manage wide variety of data at high speed, a tri-hybrid storage system has been proposed with using storage ... [more] | CPM2016-77 ICD2016-38 IE2016-72 pp.7-10 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 11:20 |
Kanagawa | Hiyoshi Campus, Keio University | An Architectural Optimization for Software Defined SSD using Full System Simulator Shun Gokita, Satoshi Kazama, Seiki Shibata, Shinya Kuwamura, Eiji Yoshida, Junji Ogawa (FLL) VLD2015-103 CPSY2015-135 RECONF2015-85 |
In recent years, a kind of software-defined SSD which has a Flash control layer (FTL) in software teared out of hardware... [more] | VLD2015-103 CPSY2015-135 RECONF2015-85 pp.197-202 |
| DC | 2015-12-18 14:00 |
Niigata | Kurieito Mulakami (Murakami City) | Error Correcting Codes Considering P/E Cycles for NAND Flash Memories Mampei Asai, Masato Kitakami (Chiba Univ.) DC2015-76 |
I Recently, multi-level cell (MLC) NAND flash memory, which has memory cells capable to store 2 or more bits of informat... [more] | DC2015-76 pp.17-22 |
| ICD, CPSY | 2015-12-17 16:00 |
Kyoto | Kyoto Institute of Technology | [Poster Presentation]
Performance Evaluation of Solid-State-Drives (SSDs) by Considering the effect of Error-correcting code Yusuke Yamaga, Tsukasa Tokutomi, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2015-71 CPSY2015-84 |
In the NAND flash memory based solid-state drives (SSDs), reliability is guaranteed by error correcting code (ECC). Conv... [more] | ICD2015-71 CPSY2015-84 p.41 |
| ICD, CPSY | 2015-12-17 16:00 |
Kyoto | Kyoto Institute of Technology | [Poster Presentation]
The Evaluation of Hybrid SSD performance Dependency on the Data Acces pattern Yusuke Sugiyama, Tomoaki Yamada, Ken Takeuchi (Chuo univ.) ICD2015-72 CPSY2015-85 |
Hybrid Solid-state drive (SSD) is comprised of NAND flash memory and storage class memory (SCM). Since the performance o... [more] | ICD2015-72 CPSY2015-85 p.43 |
| ICD, CPSY | 2015-12-17 16:00 |
Kyoto | Kyoto Institute of Technology | [Poster Presentation]
Reliability Evaluation of Privacy Protection with NAND Flash Memories Kazuki Maeda, Hiroki Yamazawa, Ken Takeuchi (Chuo Univ.) ICD2015-74 CPSY2015-87 |
Recently, Internet-data’s “Right to be forgotten” has been established for the privacy protection of personal informatio... [more] | ICD2015-74 CPSY2015-87 p.47 |
| ICD, CPSY | 2015-12-17 16:00 |
Kyoto | Kyoto Institute of Technology | [Poster Presentation]
Bit-Error Analysis in TLC NAND flash memories. Yoshiaki Deguchi, Tsukasa Tokutomi, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2015-75 CPSY2015-88 |
The capacity of NAND flash memory can be expanded by increasing the bit density. In particular, 3-bit/cell triple-level ... [more] | ICD2015-75 CPSY2015-88 p.49 |
| ICD, CPSY | 2015-12-17 16:00 |
Kyoto | Kyoto Institute of Technology | [Poster Presentation]
Error Tendency Analysis in NAND Flash Memory Yoshio Nakamura, Tomoko Ogura Iwasaki, Ken Takeuchi (Chuo Univ.) ICD2015-76 CPSY2015-89 |
Program-disturb and data-retention degrade the reliability of NAND flash memory. During program-disturb, VTH of the memo... [more] | ICD2015-76 CPSY2015-89 p.51 |
| ICD, CPSY | 2015-12-17 16:00 |
Kyoto | Kyoto Institute of Technology | [Poster Presentation]
Error Pattern Analysis of Long-Term Storage with NAND Flash Memory Tomonori Takahashi, Senju Yamazaki, Ken Takeuchi (Chuo Univ.) ICD2015-77 CPSY2015-90 |
NAND flash memory has advantages of fast access speed and high density compared with other storage devices such as hard ... [more] | ICD2015-77 CPSY2015-90 p.53 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2015-08-05 16:15 |
Oita | B-Con Plaza (Beppu) | Fragmentation-aware Write Optimization for Flash SSDs Shugo Ogawa, Takuya Araki (NEC) CPSY2015-32 |
Flash SSDs are becoming available to the purpose of storing stream data from many devices with an increase in capacity a... [more] | CPSY2015-32 pp.173-178 |
| ICD | 2015-04-16 16:05 |
Nagano | [Invited Lecture]
A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology Mario Sako, Takao Nakajima, Junpei Sato, Kazuyoshi Muraoka, Masaki Fujiu, Fumihiro Kono, Michio Nakagawa, Masami Masuda, Koji Kato, Yuri Terada, Yuki Shimizu, Mitsuaki Honma, Yoshinao Suzuki, Yoshihisa Watanabe (Toshiba), Ryuji Yamashita (SanDisk) ICD2015-6 |
A 75mm2 low power 64Gb MLC NAND flash memory capable of 30MB/s program throughput and 533MB/s data transfer rate at 1.8V... [more] | ICD2015-6 pp.27-30 |
|
| NS | 2015-01-23 12:50 |
Tokyo | Hachijo-cho-City-Hall | An energy saving method for mobile devices by utilizing flash storage and a TCP/IP offload wireless LAN interface Hiroshi Nishimoto, Yuichiro Oyama, Takaomi Murakami, Takeshi Ishihara, Kotaro Ise (Toshiba) NS2014-170 |
Energy consumption during wireless communication has been a significant issue for mobile devices such as smart phones an... [more] | NS2014-170 pp.45-50 |
| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
A High-Performance Solid-State Drives with LBA Scrambler Tomoaki Yamada, Chao Sun, Ken Takeuchi (Chuo Univ.) ICD2014-87 CPSY2014-99 |
In the NAND flash memory based Solid-state drives (SSDs), since in-place overwrite is prohibited in NAND flash, the oper... [more] | ICD2014-87 CPSY2014-99 p.53 |
| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
Performance Analysis of the Hybrid SSDs in Consideration of Error-correcting code Hirofumi Takishita, Shuhei Tanakamaru, Takahiro Onagi, Ken Takeuchi (Chuo Univ) ICD2014-88 CPSY2014-100 |
The performance of SSDs is guaranteed by error-correcting code (ECC). The longer parity size of ECC is, the higher error... [more] | ICD2014-88 CPSY2014-100 p.55 |
| CPSY | 2014-10-10 13:25 |
Chiba | Meeting Room 303, International Conference Hall, Makuhari-Messe | Theoretical Write Amplification Analysis of the SSD Shin-ichi Kanno, Hiroshi Yao (TOSHIBA), Daisuke Hashimoto (TAEC) CPSY2014-51 |
Theoretical limitation of write amplification and write speed of solid state drives (SSDs) are affected by page size and... [more] | CPSY2014-51 pp.25-30 |
| ICD | 2014-04-17 10:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
66.3KIOPS-Random-Read 690MB/s-Sequential-Read Universal Flash Storage Device Controller with Unified Memory Extension Kenichiro Yoshii, Konosuke Watanabe, Nobuhiro Kondo, Kenichi Maeda, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki (Toshiba) ICD2014-2 |
The world’s first embedded NAND storage device controller with Unified Memory (UM) has been demonstrated. UM achieves 2 ... [more] | ICD2014-2 pp.3-8 |
[Return to Top Page]