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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2024-03-22 10:15 |
Nagasaki | Ikinoshima Hall (Primary: On-site, Secondary: Online) |
Context Cache Design for Multicore RISC-V Processors Akira Yamazawa (Keio Univ), Tsutomu Itou, Suito Kazutoshi (AXELL), Nobuyuki Yamasaki (Keio Univ)  CPSY2023-44 DC2023-110 |
Today, programs are executed using multiple threads. When multiple threads are used for execution, a context switch occu... [more] | CPSY2023-44 DC2023-110 pp.35-40 |
| HWS, VLD [detail] | 2021-03-04 09:30 |
Online | Online | Design space exploration on low energy embedded multi-core processors Sayuri Onagi, Yuko Hara (Tokyo Tech) VLD2020-79 HWS2020-54 |
Nowadays, edge computing has been sought by increasing stream data and demand for real time processing so that distribut... [more] | VLD2020-79 HWS2020-54 pp.61-66 |
| R | 2015-10-16 11:00 |
Fukuoka | Irregularity Countermeasures in Massively Parallel BigData Processors Marat Zhanikeev (Kyutech) R2015-53 |
The term Massively Parallel BigData Processor names a recent advance in bigdata processing technology which has advanced... [more] | R2015-53 pp.7-14 |
|
| MSS, SS | 2013-03-07 11:20 |
Fukuoka | Shikanoshima | Multicore scheduling analysis with task migration Takayuki Nakadozono, Shoji Yuen (Nagoya Univ.) MSS2012-77 SS2012-77 |
We extend the task automata to be capable to handle ’taskmigration’. The task automata has been proposed as a general be... [more] | MSS2012-77 SS2012-77 pp.103-108 |
| CPSY | 2012-10-12 15:10 |
Hiroshima | Shared Data Management Scheme for Java Layer-Unified Coarse Grain Task Parallel Processing Yuuki Ochi, Akimasa Yoshida (Toho Univ.) CPSY2012-39 |
In parallel processing on multicore processors, the layer-unified coarse grain task parallel processing scheme, which ex... [more] | CPSY2012-39 pp.49-54 |
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| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2012-03-02 15:45 |
Miyagi | Design and implementation of distributed TLB mechanism for heterogeneous multi-core processors Daiki Kawase, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) CPSY2011-84 DC2011-88 |
Heterogeneous multi-core architecture, in which processor cores, memory modules, and I/O modules with various sizes, fu... [more] |
CPSY2011-84 DC2011-88 pp.85-90 |
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| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2012-03-03 13:30 |
Miyagi | A Case Study of Supervisor Processor for Dependable System Makoto Fujino, Yoshihiro Ichinomiya, Hiroki Tanaka, Sayaka Yoshiura, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2011-92 DC2011-96 |
Multicore processor is widely used in various systems. Although it will be used in harsh environment such as in-vehicle... [more] |
CPSY2011-92 DC2011-96 pp.199-204 |
|
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:30 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-73 ICD2011-76 IE2011-72 |
Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-... [more] | SIP2011-73 ICD2011-76 IE2011-72 pp.73-76 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:55 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-74 ICD2011-77 IE2011-73 |
Accelerator cores in low-power heterogeneous multicore processors have multiple memory modules to increase the data acce... [more] | SIP2011-74 ICD2011-77 IE2011-73 pp.77-82 |
| CPSY | 2011-10-21 10:40 |
Hyogo | Java Layer-Unified Coarse Grain Task Parallel Processing on Multicore Processors Akimasa Yoshida, Tomohiro Ozawa (Toho Univ.) CPSY2011-28 |
In parallel processing on multicore processors, the layer-unified coarse grain task parallel processing scheme, which ex... [more] | CPSY2011-28 pp.19-24 |
|
| SR | 2010-05-20 13:15 |
Kanagawa | Keio Univ. (Tokyo) | Simultaneous Multistandard Base Stations
-- A Software-Defined Multicore Approach -- Kambiz Homayounfar, Bijan Rohani, Khoo Kiak Wei (PHYBIT) SR2010-5 |
This paper addresses the challenge of implementing the uplink physical layer of LTE and WiMAX standards on a hardware pl... [more] | SR2010-5 pp.29-32 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 11:45 |
Osaka | Shoushin Kaikan | Local Memory Management Scheme by a Compiler for Multicore Processor Taku Momozono, Hirofumi Nakano, Masayoshi Mase, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
This paper proposes a local memory management scheme for an automatic parallelizing compiler to realize effective use o... [more] | ICD2008-141 pp.69-74 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2009-01-14 14:45 |
Osaka | Shoushin Kaikan | A Power Saving Scheme on Multicore Processors Using OSCAR API Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara (Waseda Univ.) |
Effective power reduction of an application program on multicore processors requires appropriate power control for each ... [more] | ICD2008-145 pp.93-98 |
| ICD, IPSJ-ARC | 2008-05-14 09:30 |
Tokyo | Design and Evaluation of a Heterogeneous Multicore SoC with 9 CPUs and 2 Matrix Processors Masami Nakajima, Koichi Ishimi, Naoto Okumura, Norio Masui, Osamu Yamamoto, Hiroyuki Kondo (Renesas) ICD2008-26 |
A multicore SoC has been developed for various applications (recognition, inference, measurement, control and security) ... [more] | ICD2008-26 pp.45-50 |
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| CPSY | 2007-10-26 09:40 |
Kumamoto | Kumamoto University | Performance, Power, and Dependability Trade-off on Multiple Clusterd Core Processors Toshinori Sato (Kyushu Univ.), Toshimasa Funaki (Kyushu Inst Tech) CPSY2007-31 |
As deep submicron technologies are advanced, we face new challenges, such as power consumption and soft errors. A na... [more] | CPSY2007-31 pp.39-44 |
| NS, CS, IN (Joint) |
2007-09-20 16:50 |
Miyagi | Tohoku University | Parallel Packet Processing Method Using MultiCore Processor Satoshi Kurosawa, Tsuyoshi Mikoda, Keiji Okubo (Mitsubishi Electric Co.) NS2007-66 |
Recently, a demand of high-speed IP packet processing is increasing, according to the widespread of the broadband access... [more] | NS2007-66 pp.69-72 |
| IPSJ-AVM, MoNA | 2007-07-19 15:40 |
Niigata | Niigata Univ. | Parallelization of H.264 Video Decoder for Embedded Multicore Processor Kosuke Nishihara, Atsushi Hatabu, Tatsuji Moriyoshi (NEC) MoMuC2007-29 |
H.264 video codec, which is widely-used for mobile devices, requires higher workload than previous standards. Thus a hig... [more] | MoMuC2007-29 pp.25-30 |
| ICD, IPSJ-ARC | 2007-05-31 13:45 |
Kanagawa | Mutligrain Parallel Processing in SMP Execution Mode on a Multicore for Consumer Electronics Masayoshi Mase, Daisuke Baba, Harumi Nagayama, Hiroaki Tano, Takeshi Masuura, Takamichi Miyamoto, Jun Shirako, Hirofumi Nakano, Keiji Kimura (Waseda Univ.), Tatsuya Kamei, Toshihiro Hattori, Atsushi Hasegawa (Renesas Technology), Masaki Ito, Makoto Satoh, Kunio Uchiyama (Hitachi Ltd.) |
Currently, multicore processors are becoming ubiquitous in various computing domains, namely con- sumer electronics suc... [more] |
ICD2007-21 pp.25-30 |
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