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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control Yusuke Yoshida, Kimiyoshi Usami (SIT)  VLD2017-33 DC2017-39 |
Embedded memory macros are major central building blocks of any microprocessor and greatly affect power dissipation. In ... [more] | VLD2017-33 DC2017-39 pp.37-42 |
| RECONF | 2017-09-25 14:20 |
Tokyo | DWANGO Co., Ltd. | A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization Tomoya Fujii, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.) RECONF2017-26 |
For a pre-trained deep convolutional neural network (CNN) for an embedded system, a high-speed and a low power consumpt... [more] |
RECONF2017-26 pp.25-30 |
| ICD | 2017-04-20 16:10 |
Tokyo | [Invited Talk]
A 512Gb 3b/Cell Flash Memory on 64-Word-Line-Layer BiCS Technology Ryuji Yamashita, Sagar Magia (WDC), Tsutomu Higuchi, Kazuhide Yoneya, Toshio Yamamura (Toshiba), Hiroyuki Mizukoshi, Shingo Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang (WDC) ICD2017-9 |
A 512Gb 3b/cell flash has been developed on a 64-WL-layer BiCS technology. By using a four-block-EOC row decoding approa... [more] | ICD2017-9 pp.45-50 |
|
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Reduction of Data-Retention Error in TLC NAND Flash Memories Yuichi Sato, Yoshiaki Deguchi, Atsuro Kobayashi, Ken Takeuchi (Chuo Univ.) ICD2016-76 CPSY2016-82 |
The cost of NAND flash memory is reduced by scaling and multi-level cell technologies. However, the reliability of tripl... [more] | ICD2016-76 CPSY2016-82 p.75 |
| VLD, CAS, MSS, SIP | 2016-06-17 09:50 |
Aomori | Hirosaki Shiritsu Kanko-kan | Design and Evaluation of MTJ-based Standard Cell Memory Junya Akaike, Masaru Kudo, Kimiyoshi Usami (SIT) CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 |
With the spread of portable devices, products with high performance and long battery life are required. In this paper, w... [more] | CAS2016-19 VLD2016-25 SIP2016-53 MSS2016-19 pp.103-108 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 14:15 |
Kanagawa | Hiyoshi Campus, Keio University | Write-Reduction using Encoding data on MLC for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-107 CPSY2015-139 RECONF2015-89 |
There is a movement to use the non-volatile memory to the important main memory in von Neumann computer. Non-volatile m... [more] |
VLD2015-107 CPSY2015-139 RECONF2015-89 pp.221-225 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.) CPSY2015-72 |
Current CPU utilizes cache memory for decreasing an access speed gap between CPU and main memory. But the cache occupie... [more] |
CPSY2015-72 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement Junya Goto, Nagisa Ishiura (K.G.) VLD2015-74 DC2015-70 |
This article proposes a method of reducing cache misses on an instruction memory by inserting offsets before basic block... [more] | VLD2015-74 DC2015-70 pp.237-241 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 15:00 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-76 DC2015-72 |
Recently, due to low leakage power and non-volatility, the non-volatile memory technology has advanced remarkably. Howe... [more] |
VLD2015-76 DC2015-72 pp.249-253 |
| ICD, IE, VLD, IPSJ-SLDM [detail] | 2015-10-26 15:25 |
Miyagi | A Power-Efficient Memory Hierarchy Design for the 3D Integration Era Wataru Uno, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.) VLD2015-30 ICD2015-43 IE2015-65 |
3D-stacked memories are expected to play key roles to realize high-performance and low-power computing systems. This pap... [more] | VLD2015-30 ICD2015-43 IE2015-65 pp.19-24 |
|
| ICD | 2015-04-16 16:05 |
Nagano | [Invited Lecture]
A Low-Power 64Gb MLC NAND-Flash Memory in 15nm CMOS Technology Mario Sako, Takao Nakajima, Junpei Sato, Kazuyoshi Muraoka, Masaki Fujiu, Fumihiro Kono, Michio Nakagawa, Masami Masuda, Koji Kato, Yuri Terada, Yuki Shimizu, Mitsuaki Honma, Yoshinao Suzuki, Yoshihisa Watanabe (Toshiba), Ryuji Yamashita (SanDisk) ICD2015-6 |
A 75mm2 low power 64Gb MLC NAND flash memory capable of 30MB/s program throughput and 533MB/s data transfer rate at 1.8V... [more] | ICD2015-6 pp.27-30 |
|
| VLD | 2015-03-03 16:15 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-173 |
Non-volatile memory is superior to SRAM in terms of its high density and low leakage power but it consumes larger writ... [more] |
VLD2014-173 p.115 |
| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
A High-Performance Solid-State Drives with LBA Scrambler Tomoaki Yamada, Chao Sun, Ken Takeuchi (Chuo Univ.) ICD2014-87 CPSY2014-99 |
In the NAND flash memory based Solid-state drives (SSDs), since in-place overwrite is prohibited in NAND flash, the oper... [more] | ICD2014-87 CPSY2014-99 p.53 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita | B-ConPlaza | Energy evaluation of bit-write reduction method based on state encoding limiting maximum and minimum Hamming distances for non-volatile memories Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-105 DC2014-59 |
Data stored in non-volatile memories may be destructed due to crosstalk and radiation but we can restore their data by u... [more] | VLD2014-105 DC2014-59 pp.221-226 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-106 DC2014-60 |
Non-volatile memory has many advantages such as low leakage power and non-volatility. However, there are problems that ... [more] |
VLD2014-106 DC2014-60 pp.227-232 |
| SDM | 2014-11-06 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Device simulation
-- More than 30 years in Toshiba's TCAD -- Naoyuki Shigyo (Toshiba) SDM2014-100 |
TCAD is one of important tools for designing a semiconductor device. As a virtual fabrication, TCAD contributes to reduc... [more] | SDM2014-100 pp.25-30 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 13:40 |
Hokkaido | Hokkaido University | Write Reduction of Internal Registers for Non-volatile RISC Processors Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 |
Recently next-generation non-volatile memories based on MTJ (Magnetic Tunnel Junction) have been paid attention because ... [more] | CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 pp.213-218 |
| ICD | 2014-04-17 12:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of Exchangeable MLC/TLC Hybrid Storage Array for Big Data Shogo Hachiya, Koh Johguchi (Chuo Univ.), Kousuke Miyaji (Shinshu Univ.), Ken Takeuchi (Chuo Univ.) ICD2014-5 |
A TLC-NAND flash provides a low cost and high capacity memory solution. However the reliability and access latency of TL... [more] | ICD2014-5 pp.21-26 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 15:15 |
Kanagawa | Hiyoshi Campus, Keio University | A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84 |
In order to reduce the power consumption of LSI, unnecessary parts should be powered off with fine granularity, and c... [more] |
VLD2013-130 CPSY2013-101 RECONF2013-84 pp.167-172 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:50 |
Kagoshima | Energy evaluation of writing reduction method for non-volatile memory Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-81 DC2013-47 |
Non-volatile memory has many advantages over SRAM, such as high density, low leakage power, and non-volatility. However... [more] |
VLD2013-81 DC2013-47 pp.141-146 |
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