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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2018-12-05
11:00		 Hiroshima Satellite Campus Hiroshima [Keynote Address] Challenge of Post CMOS Circuit Technologies for AI Hardware
Takahiro Hanyu (Tohoku Univ.) 		Recently, it is impartant that the impact of artificial intelligence (AI) is being widely understood in several applicat... [more]
ICD 2014-04-17
15:15		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Lecture] Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine
Shoun Matsunaga (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi (NEC), Masanori Natsui, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2014-8		 We demonstrate a 1-Mb nonvolatile TCAM-based search engine using 90-nm CMOS and perpendicular MTJ technologies for an ul... [more] ICD2014-8
pp.39-44
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-27
13:25		 Kagoshima   A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu (Tohoku Univ.) CPM2013-116 ICD2013-93		 In this paper, a design methodology for realizing power efficient nonvolatile FPGA (NVFPGA) using magnetic tunnel juncti... [more] CPM2013-116 ICD2013-93
pp.49-53
ICD 2010-04-22
15:20		 Kanagawa Shonan Institute of Tech. Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array
Daisuke Suzuki, Masanori Natsui, Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa (ARL, Hitachi, Ltd.), Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2010-9		 This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnet... [more] ICD2010-9
pp.47-52
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