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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2015-01-27 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba)  SDM2014-142 |
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] | SDM2014-142 pp.29-32 |
| MRIS, ITE-MMS | 2014-10-03 09:30 |
Niigata | Kashiwazaki energy hall, Niigata | * Daisuke Saida, Naoharu Shimomura, Eiji Kitagawa, Chikayoshi Kamata, Megumi Yakabe, Yuuichi Osawa, Shinobu Fujita, Junichi Ito (Toshiba) MR2014-18 |
(To be available after the conference date) [more] | MR2014-18 pp.27-31 |
| ICD, SDM | 2014-08-04 13:55 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
STT-MRAM Development for Embedded Cache Memory Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP) SDM2014-68 ICD2014-37 |
We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration ... [more] | SDM2014-68 ICD2014-37 pp.35-38 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 13:40 |
Hokkaido | Hokkaido University | Write Reduction of Internal Registers for Non-volatile RISC Processors Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 |
Recently next-generation non-volatile memories based on MTJ (Magnetic Tunnel Junction) have been paid attention because ... [more] | CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 pp.213-218 |
| ICD | 2014-04-17 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Panel Discussion]
Perspective of emerging memories in systems and systems on emerging memories Toru Miwa (SanDisk), Koji Nii (Renesas), Shinobu Fujita (Toshiba), Hiroki Koike (Tohoku Univ.), Ken Takeuchi (Chuo Univ.) ICD2014-9 |
(To be available after the conference date) [more] | ICD2014-9 p.45 |
| ICD | 2014-04-18 09:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A 0.38-V Operating STT-MRAM with Process Variation Tolerant Sense Amplifier Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Koji Tsunoda, Toshihiro Sugii (LEAP) ICD2014-10 |
This paper exhibits a 65-nm 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a s... [more] | ICD2014-10 pp.47-51 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 15:15 |
Kanagawa | Hiyoshi Campus, Keio University | A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84 |
In order to reduce the power consumption of LSI, unnecessary parts should be powered off with fine granularity, and c... [more] |
VLD2013-130 CPSY2013-101 RECONF2013-84 pp.167-172 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
STT-MRAM Architecture for Improving Throughput Haruki Mori, Koji Yanagida, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Koji Tsunoda, Toshihiro Sugii (LEAP) ICD2013-110 |
STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory) attracts an attention as the substitute memory of SRAM. Th... [more] | ICD2013-110 p.27 |
| MRIS, ITE-MMS | 2013-07-12 16:35 |
Tokyo | Chuo Univ. | Progress on STT MTJ writing Technology and the Effect on Normally-off Computing Systems Junichi Ito, Hiroaki Yoda, Shinobu Fujita, Naoharu Shimomura, Eiji Kitagawa, Keiko Abe, Kumiko Nomura, Hiroki Noguchi (Toshiba) MR2013-13 |
We propose a new processor using STT-MRAMs as cache memories. It enables “Normally-off computing”, where the processor i... [more] | MR2013-13 pp.37-41 |
| ICD | 2013-04-11 09:50 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Talk]
A Novel MTJ for STT-MRAM with a Dummy Free Layer and Dual Tunnel Junctions Koji Tsunoda, Hideyuki Noshiro, Chikako Yoshida, Yuuichi Yamazaki, Atsushi Takahashi, Yoshihisa Iba, Akiyoshi Hatada, Masaaki Nakabayashi, Takashi Takenaga, Masaki Aoki, Toshihiro Sugii (LEAP) ICD2013-2 |
A novel magnetic tunnel junction (MTJ) for embedded memory applications such as spin transfer torque magneto-resistive r... [more] | ICD2013-2 pp.5-10 |
| ICD | 2013-04-11 17:30 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Panel Discussion]
Future prospects of memory solutions for smart society
-- Can new nonvolatile memories replace SRAM/DRAM/Flash? -- Koji Nii (Renesas Erctronics), Tetsuo Endoh (Tohoku Univ.), Yoshikazu Katoh (Panasonic), Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (Elpida Memory), Atsushi Kawasumi (Toshiba), Toru Miwa (SanDisk) ICD2013-11 |
(To be available after the conference date) [more] | ICD2013-11 p.53 |
| ICD | 2012-12-17 13:30 |
Tokyo | Tokyo Tech Front | [Invited Talk]
High-performance STT-MRAM and Its Integration for Embedded Application Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LESP) ICD2012-90 |
High-performance spin transfer torque MRAM (STT-MRAM) for embedded cache memories was developed, utilizing a top-pinned ... [more] | ICD2012-90 pp.17-20 |
| IPSJ-SLDM, SIP, IE, ICD [detail] | 2010-10-05 13:20 |
Chiba | Makuhari Messe, International Conference Hall | Study of stacked NOR type MRAM using spin transistor Shouto Tamai, Shigeyoshi Watanabe (sit) SIP2010-55 ICD2010-69 IE2010-73 |
In this paper stacked NOR type MRAM with vertical spin transistor has been newly proposed. Word line scheme surrounded b... [more] | SIP2010-55 ICD2010-69 IE2010-73 pp.37-42 |
| ICD, SDM | 2010-08-27 11:40 |
Hokkaido | Sapporo Center for Gender Equality | Study of stacked MRAM for universal memory Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-142 ICD2010-57 |
In this paper stacked NOR type MRAM with vertical spin transistor has been newly proposed. Word line scheme surrounded b... [more] | SDM2010-142 ICD2010-57 pp.99-104 |
| ICD | 2010-04-22 13:30 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
A 64Mbit MRAM with Clamped-Reference and Adequate-Reference Schemes Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe (TOSHIBA) ICD2010-7 |
A 64Mb spin-transfer-torque MRAM in 65nm CMOS is developed. 47mm2 die uses 0.3584um2 cell with the perpendicular-TMR dev... [more] | ICD2010-7 pp.35-40 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Design Technology of stacked NAND type MRAM Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-79 |
Design technology of stacked type MRAM using spin transistor has been described. Using 64 layer level cell structure fea... [more] | ICD2009-79 pp.19-23 |
| ITE-MMS, MRIS | 2009-10-08 13:55 |
Fukuoka | FUKUOKA traffic center | [Invited Talk]
Nonvolatile RAM using spin transfer torque magnetization reversal (SPRAM) Hiromasa Takahashi, Kenchi Ito, Jun Hayakawa, Katsuya Miura, Hiroyuki Yamamoto, Michihiko Yamanouchi (ARL, Hitachi, Ltd.), Kazuo Ono, Riichiro Takemura, Takayuki Kawahara (CRL, Hitachi, Ltd.), Ryutaro Sasaki (RIEC Tohoku Univ.), Haruhiro Hasegawa (RIEC Tohoku Univ., ARL, Hitachi, Ltd.), Shoji Ikeda (RIEC Tohoku Univ.), Hideyuki Matsuoka (ARL, Hitachi, Ltd.), Hideo Ohno (RIEC Tohoku Univ.) |
The SPRAM (Spin Transfer Torque MRAM) is one of nonvolatile memories that “writing” is done by that a magnetization in M... [more] | |
| ITE-MMS, MRIS | 2009-10-09 11:35 |
Fukuoka | FUKUOKA traffic center | Stress assisted magnetization reversal of a spin valve structural perpendiculr GMR muti-layer Kazuya Jimbo, Naoya Saito, Shigeki Nakagawa (Tokyo Inst. of Tech.) MR2009-27 |
A Stress Assisted Magnetization Reversal (SAMR) method has been demonstrated in order to reduce a powerconsumption durin... [more] | MR2009-27 pp.37-40 |
| ICD, SDM | 2009-07-17 14:10 |
Tokyo | Tokyo Institute of Technology | Low Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM Shunsuke Fukami, Tetsuhiro Suzuki, Kiyokazu Nagahara, Norikazu Ohshima (NEC Corp.), Yasuaki Ozaki (NECEL Corp.), Shinsaku Saito, Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Kaoru Mori, Chuji Igarashi, Sadahiko Miura, Nobuyuki Ishiwata, Tadahiko Sugibayashi (NEC Corp.) SDM2009-114 ICD2009-30 |
We have developed a new magnetic random access memory with current-induced domain wall motion (DW-motion MRAM) using per... [more] | SDM2009-114 ICD2009-30 pp.91-95 |
| SDM, ED | 2009-06-24 15:00 |
Overseas | Haeundae Grand Hotel, Busan, Korea | Transient characteristic of fabricated Magnetic Tunnel Junction (MTJ) programmed with CMOS circuit Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda (Tohoku Univ.), Katsuya Miura (Tohoku Univ./Hitachi), Jun Hayakawa (Hitachi), Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ED2009-52 SDM2009-47 |
In this paper, it is shown that our fabricated MTJ of 60x180${\rm nm^2}$, which is connected to the MOSFET in series by ... [more] | ED2009-52 SDM2009-47 pp.9-12 |
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