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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2024-04-11 13:50 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A 22 nm 10.8 Mb Embedded STT MRAM Macro Achieving over 200 MHz Random Read Access and a 10.4 MB/s Write Throughput for High End MCUs Masayuki Izuna, Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono (Renesas Electronics)  ICD2024-6 |
(To be available after the conference date) [more] | ICD2024-6 pp.18-19 |
| ICD | 2024-04-11 14:30 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing Kenta Suzuki, Keizo Hiraga, Bessho Kazuhiro (Sony), Kimiyoshi Usami (SIT), Taku Umebayashi (Sony) ICD2024-7 |
(To be available after the conference date) [more] | ICD2024-7 pp.20-23 |
| MRIS, ITE-MMS | 2023-06-08 14:20 |
Miyagi | Tohoku Univ. （RIEC) (Primary: On-site, Secondary: Online) |
[Invited Talk]
Computing in pursuit of energy efficiency
-- From the perspective of non-volatile memory circuits using MTJ -- Kimiyoshi Usami (Shibaura IT) MRIS2023-3 |
From AlphaGo which defeated a professional human GO player up to automatic driving of cars and the very recent ChatGPT, ... [more] | MRIS2023-3 pp.13-20 |
| ICD | 2023-04-10 11:00 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono (Renesas Electronics) ICD2023-2 |
This paper presents a high-precision sense amplifier and a fast write throughput technique of a 32Mb embedded STT-MRAM m... [more] | ICD2023-2 p.7 |
| ICD | 2023-04-11 15:15 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Talk]
Development trends of embedded MRAM IP for MCU Applications Tomoya Saito (Renesas) ICD2023-12 |
(To be available after the conference date) [more] | ICD2023-12 p.29 |
| ICD | 2023-04-11 16:05 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Keynote Address]
Game Change by Spintronics Low Power semiconductors and its contribution to a carbon-neutral society
-- from STT/SOT-MRAM to its application to IoT/AI processors -- Tetsuo Endoh (Tohoku Univ.) ICD2023-13 |
[more] | ICD2023-13 p.30 |
| SDM | 2023-01-30 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. B3-1 | [Invited Talk]
25 nm iPMA-type Hexa-MTJ with solder reflow capability and endurance >107 for eFlash-type MRAM H Honjoi, K Nishioka, S Miura, Hiroshi Naganuma, T Watanabe, T Nasuno, T Tanigawa, Y Noguchi, H Inoue, M Yasuhiro, S Ikeda, T Endoh (Tohoku Univ.) SDM2022-81 |
A solder reflow capable eflash-type MRAM was realized by interfacial perpendicular magnetic anisotropy Hexa-CoFeB/MgO-in... [more] | SDM2022-81 pp.9-12 |
| SDM | 2022-01-31 13:15 |
Online | Online | [Invited Talk]
**** Tomoya Saito, Takashi Ito, Yasuhiko Taito, Kenichiro Sonoda, Genta Watanabe, Ken Matsubara, Akihiko Kanda, Takahiro Shimoi, Koichi Takeda, Takashi Kono (Renesas) SDM2021-68 |
We present the low energy write techniques and measurement results of a 20Mb embedded STT-MRAM test chip in 16nm FinFET ... [more] | SDM2021-68 pp.1-4 |
| HWS, VLD [detail] | 2021-03-03 10:00 |
Online | Online | Energy Efficient Approximate Storing to MRAM for Deep Neural Network Tasks in Edge Computing Yoshinori Ono, Kimiyoshi Usami (SIT) VLD2020-67 HWS2020-42 |
On-chip learning is gaining attention in edge devices. In addition, a magnetic RAM (MRAM) is a promising memory technolo... [more] | VLD2020-67 HWS2020-42 pp.1-6 |
| MRIS, ITE-MMS | 2020-10-05 14:20 |
Online | Online | Recent progress on piezo-electronic magnetoresistive devices using giant magnetostrictive SmFe2 thin films Soki Urashita, Hayato Onozawa, Ryota Kitagawa, Masato Tomita, Takashi Harumoto, Ji Shi, Yoshio Nakamura, Yota Takamura, Shigeki Nakagawa (Tokyo Tech.) MRIS2020-3 |
In magnetic tunnel junctions (MTJs) for magnetoresistive random access memory, a trade-off relationship between the crit... [more] | MRIS2020-3 pp.12-15 |
| MRIS, ITE-MMS | 2018-12-06 15:30 |
Ehime | Ehime University | Simulation analysis of the write error rate of voltage-torque MRAM Hiroshi Imamura (AIST) MRIS2018-23 |
Voltage torque MRAM, where the information is written by using the voltage control of the magntic anisotropy, has attrac... [more] | MRIS2018-23 pp.19-23 |
| MRIS, ITE-MMS | 2017-07-07 16:10 |
Tokyo | Tokyo Tech | Voltage-Control Spintronics Memory (VoCSM) Altansargai Buyandalai, Hiroaki Yoda, Mariko Shimizu, Tomoaki Inokuchi, Yuichi Ohsawa, Naoharu Shimomura, Satoshi Shirotori, Hideyurki Sugiyama, Yushi Kato, Yuuzo Kamiguchi, Katsuhiko Koi, Soichi Oikawa, Mizue Ishikawa, Yoshiaki Saito, Atsushi Kurobe (Toshiba Corp.) MR2017-16 |
We propose a new spintronics-based memory VoCSM (Voltage-control Spintronics Memory) employing the voltage-control-magne... [more] | MR2017-16 pp.37-40 |
| ICD | 2017-04-20 10:35 |
Tokyo | [Invited Lecture]
Sub-3 ns pulse with sub-100 uA switching of 1x-2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS Daisuke Saida, Saori Kashiwaad, Megumi Yakabe, Tadaomi Daibou, Junichi Ito, Hiroki Noguchi, Keiko Abe, Shinobu Fujita (Toshiba), Miyoshi Fukumoto, Shinji Miwa, Yoshishige Suzuki (Osaka Univ.) ICD2017-2 |
[more] | ICD2017-2 pp.5-9 |
|
| ICD | 2017-04-20 11:00 |
Tokyo | [Invited Talk]
A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture Kenji Tsuchida (Toshiba), Kwangmyoung Rho, Dongkeun Kim (SK hynix), Yutaka Shirai (Toshiba), Jihyae Bae (SK hynix), Tsuneo Inaba, Hiromi Noro (Toshiba), Hyunin Moon, Sungwoong Chung (SK hynix), Kazumasa Sunouchi (Toshiba), Jinwon Park, Kiseon Park (SK hynix), Akihito Yamamoto (Toshiba), Seoungju Chung, Hyeongon Kim (SK hynix) ICD2017-3 |
The experimental 4-Gbit STT-MRAM with 9F2 1T1MTJ cell of 90nm by 90nm is presented. Hierarchical bit line architecture a... [more] | ICD2017-3 pp.11-16 |
|
| SDM | 2017-01-30 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Novel Voltage Controlled MRAM (VCM) with Fast Read/Write Circuits for Ultra Large Level Cache Yoichi Shiota (AIST), Hiroki Noguchi, Kazutaka Ikegami, Keiko Abe, Shinobu Fujita (Toshiba), Takayuki Nozaki, Shinji Yuasa (AIST), Yoshishige Suzuki (Osaka Univ.) SDM2016-135 |
In future processing system, the memory capacity of last level cache (LLC) must be increased, because LLC needs to cover... [more] | SDM2016-135 pp.21-24 |
| MRIS, ITE-MMS | 2016-10-20 14:00 |
Fukuoka | Nishijin Plaza | Numerical simulation for inductive detection of magnetic vortex core rotation and polarity switching Xiaorui Ya, Terumitsu Tanaka, Kimihide Matsuyama (Kyushu Univ.) MR2016-23 |
This study describes micromagnetic simulations of vortex core rotations and its polarity switching induced by circularly... [more] | MR2016-23 pp.19-22 |
| ICD | 2016-04-14 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Tosinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2016-10 |
A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array with a high-signal-... [more] | ICD2016-10 pp.51-56 |
| SDM | 2016-01-28 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
MTJ based "Normally-off processors" with thermal stability factor engineered perpendicular MTJ, L2 cache based on 2T-2MTJ cell, L3 and Last Level Cache based on 1T-1MTJ cell and novel error handling scheme Kazutaka Ikegami, Hiroki Noguchi, Satoshi Takaya, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Eiji Kitagawa, Takao Ochiai, Naoharu Shimomura, Daisuke Saida, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba) SDM2015-126 |
MTJ-based cache memory is expected to reduce processor power significantly. However, write energy increases rapidly for ... [more] | SDM2015-126 pp.27-30 |
| MRIS, ITE-MMS | 2015-07-10 16:35 |
Tokyo | Waseda Univ. | [Invited Talk]
Current status and new materials in nonvolatile magnetic memory devices Seiji Mitani (NIMS) |
Materials research on magnetic tunnel junctions for MRAM and logic devices is overviewed, including my group activities.... [more] | |
| SDM | 2015-03-02 13:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg | [Invited Talk]
Area dependence of thermal stability factor in perpendicular STT-MRAM analized by bi-directional data flipping model Koji Tsunoda, Masaki Aoki, Hideyuki Noshiro, Yoshihisa Iba, Chikako Yoshida, Yuuichi Yamazaki, Atsushi Takahashi, Akiyoshi Hatada, Masaaki Nakabayashi, Toshihiro Sugii (LEAP) SDM2014-166 |
We report a statistical analysis of the thermal stability factor (delta) for the top-pinned perpendicular magnetic tunne... [more] | SDM2014-166 pp.23-28 |
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