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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
Phase compensation technique for low-noise small-area three-stage opamp Hicham Haibi, Ippei Akita, Makoto Ishida (Toyohashi Univ. of Tech.)  ICD2013-111 |
In this paper we present a low-noise small-area three-stage operational amplifier for biomedical arrayed sensors. Recent... [more] | ICD2013-111 p.29 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 09:20 |
Kagoshima | Design and evaluation of circuits to control scan-in power in logic BIST Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) VLD2013-93 DC2013-59 |
Power reduction during Logic BIST is a crucial problem; however, power controlling technologies are required as well as ... [more] | VLD2013-93 DC2013-59 pp.233-238 |
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| CAS, NLP | 2013-09-26 13:30 |
Gifu | Satellite Campus, Gifu University | A Study on Output Smoothing in Electric Power System with Multiple Homes using Battery Yoshihiko Yamaguchi, Yoshihiko Susuki, Takashi Hikihara (Kyoto Univ.) CAS2013-38 NLP2013-50 |
This report studies output smoothing control of an electric power system with multiple homes using battery. Output smoot... [more] | CAS2013-38 NLP2013-50 pp.13-18 |
| SDM, ICD | 2013-08-02 10:25 |
Ishikawa | Kanazawa University | 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Kazutaka Mori, Kazumasa Yanagisawa (Renesas Electronics) SDM2013-77 ICD2013-59 |
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achievi... [more] | SDM2013-77 ICD2013-59 pp.59-64 |
| DC, CPSY (Joint) |
2013-08-02 17:00 |
Fukuoka | Kitakyushu-Kokusai-Kaigijyo | Design of Variable Stages Pipeline Processor on Superscalar Processor Tomoyuki Nakabayashi, Seiji Miyoshi, Takahiro Sasaki, Toshio Kondo (Mie Univ.) CPSY2013-27 |
This paper designs a high performance and low energy superscalar processor using variable stages pipeline (VSP) techniqu... [more] | CPSY2013-27 pp.103-108 |
| ICD, ITE-IST | 2013-07-05 13:15 |
Hokkaido | San Refre Hakodate | [Invited Talk]
Design Techniques for High-Performance Continuous-Time Delta-Sigma Modulators Shiro Dosho (Panasonic) ICD2013-37 |
Along with miniaturization of CMOS-LSIs, analog-to-digital converters have been highly developed. Especially, performanc... [more] | ICD2013-37 pp.81-88 |
| ICD, ITE-IST | 2013-07-05 16:25 |
Hokkaido | San Refre Hakodate | A Intermittently Operating LNA with Optimal On-Off Controller for Pulse-Based Inductive-Coupling Transceiver Teruo Jyo, Kaoru Kohira, Yuki Urano, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.) ICD2013-42 |
This paper presents a low-power LNA for a inductive-coupling tranceiver. Intermittently operating technique to turn on L... [more] | ICD2013-42 pp.113-118 |
| MW | 2013-03-08 11:20 |
Hiroshima | Hiroshima Univ. | [Special Invited Talk]
Current Status and Future Prospect for Analog and RF CMOS Integrated Circuits Akira Matsuzawa (Tokyo Inst. of Tech.) MW2012-185 |
Current status and future prospect for analog and RF CMOS integrated circuits will be discussed. The physical relationsh... [more] | MW2012-185 p.147 |
| VLD | 2013-03-06 10:55 |
Okinawa | Okinawa Seinen Kaikan | Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating Yoshihiro Tsurui, Kimiyoshi Usami, Tatsunori Hashida, Tetsuya Muto, Yuki Shimada (Shibaura Inst. of Tech.) VLD2012-155 |
In order to perform more efficient Fine-grain Power Gating which reduces the leakage power by cutting Power Supply, it i... [more] | VLD2012-155 pp.105-110 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 10:35 |
Kanagawa | Low power packet transfer technique on distributed real-time systems Yusuke Kumura, Osamu Yoshizumi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) VLD2012-126 CPSY2012-75 RECONF2012-80 |
In this paper, we propose a low-power technique for real-time communication standard Responsive Link in which data rate ... [more] | VLD2012-126 CPSY2012-75 RECONF2012-80 pp.111-116 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Low Power Reconfiguarable Accelerator Design with Silicon on Thin Buried Oxide Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.) RECONF2012-47 |
Nowadays，with the development of low power supply voltage Vdd，it is becoming a serious issue that the bios of threshold ... [more] | RECONF2012-47 pp.3-8 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Analytical model of energy dissipation for comparing adder architectures Nao Konishi, Kimiyoshi Usami (Shibaura I.T.) VLD2012-80 DC2012-46 |
This paper describes analytical models for delay and energy dissipation of ripple-carry, carry look-ahead, and parallel ... [more] | VLD2012-80 DC2012-46 pp.123-128 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Energy Measurement and Analysis of ProcessingElement for Ultra Low Voltage Sachio Anzai, Masaru Kudo, Yuya Ota, Kazuki Ota, Kimiyoshi Usami (Sibaura Inst. Tech.) VLD2012-99 DC2012-65 |
The ALU of the ProcessingElement at 65nm process was operated by the ultra-low voltage, and delay time and survey of pow... [more] | VLD2012-99 DC2012-65 pp.231-236 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Scan-Out Power Reduction Method for Multi-Cycle BIST Senling Wang, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech) VLD2012-102 DC2012-68 |
Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on sc... [more] | VLD2012-102 DC2012-68 pp.249-254 |
| AP, RCS (Joint) |
2012-11-15 09:50 |
Tokyo | Tokyo Denki University | A Study on a Periodic Wakeup Protocol for Active Tags Mari Ochiai, Akinori Taira, Fumio Ishizu (Mitsubishi Electric) RCS2012-162 |
Periodic and regular wakeup is a common technique for reducing power consumption in active tag systems. The transmitted ... [more] | RCS2012-162 pp.7-11 |
| ICD, SDM | 2012-08-03 14:00 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | [Invited Talk]
High Efficient, Fast Load Tacking, Low EMI Wireless Power Delivery Circuits for Non-contact Memory Card Hiroki Ishikuro, Ryota Shinoda, Kazutoshi Tomita, Yuya Hasegawa (Keio Univ.) SDM2012-84 ICD2012-52 |
Watt-class wireless power delivery system for SD card size large volume memory card was developed. Fast load tracking te... [more] | SDM2012-84 ICD2012-52 pp.115-120 |
| IPSJ-SLDM, VLD | 2012-05-30 14:55 |
Fukuoka | Kitakyushu International Conference Center | Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2012-2 |
HDR architecture has been proposed as a platform that integrates energy-efficiency and interconnection delays into high-... [more] | VLD2012-2 pp.7-12 |
| RCS | 2012-04-19 16:55 |
Kyoto | Kyoto Univ. | [Requested Talk]Energy Harvesting Technology for Urine-activated Sensor System Takakuni Douseki (Ritsumeikan Univ.) RCS2012-10 |
In the era of sensor network, there will be a stronger demand for short-range wireless systems to connect things to the ... [more] | RCS2012-10 pp.55-59 |
| CAS, CS, SIP | 2012-03-08 13:45 |
Niigata | The University of Niigata | A Time-Interleave Pipelined SAR ADC Using Amplifier Sharing Technique Masanori Furuta, Taichi Ogawa, Tetsuro Itakura (Toshiba) CAS2011-128 SIP2011-148 CS2011-120 |
An eight-channel time-interleaved ADC with individual reference voltage buffers is presented. Each channel consists of b... [more] | CAS2011-128 SIP2011-148 CS2011-120 pp.121-124 |
| VLD | 2012-03-07 13:20 |
Oita | B-con Plaza | Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-138 |
This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s ... [more] | VLD2011-138 pp.109-114 |
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