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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RCS | 2017-04-24 11:20 |
Kagawa | Kotohira Onsen Kotosankaku | Efficient Radio Access for Massive Machine-Type Communication
-- Studies of Successive Interference Cancellation and Parallel Interference Cancellation -- Masafumi Moriyama, Kenichi Takizawa, Hayato Tezuka, Masayuki Oodo, Changwoo Pyo, Homare Murakami, Kentaro Ishidu, Fumihide Kojima (NICT)  RCS2017-5 |
A rapid increase of uplink traffic is predicted with the spread of IoT (Internet of Things) devices. The 5G (5th generat... [more] | RCS2017-5 pp.23-28 |
| MW, ICD | 2017-03-02 16:30 |
Okayama | Okayama Prefectural Univ. | [Invited Lecture]
An Adaptive Phased Array Control Method Using Low-Frequency Part of Signal Tuanthanh Ta (Toshiba), Suguru Kameda, Noriharu Suematsu, Tadashi Takagi, Kazuo Tsubouchi (Tohoku Univ.) MW2016-202 ICD2016-132 |
We proposed a low cost, low power consumption beam-forming technique for wide-band wireless system such as WPAN. In prop... [more] | MW2016-202 ICD2016-132 pp.79-83 |
| VLD | 2017-03-01 14:00 |
Okinawa | Okinawa Seinen Kaikan | Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines Shota Enokido, Kimiyoshi Usami (SIT) VLD2016-102 |
Non-volatile Power Gating(NVPG) is a technique to power gate memory elements to reduce leakage power while keeping the s... [more] | VLD2016-102 pp.1-6 |
| IE, ITS, ITE-AIT, ITE-HI, ITE-ME, ITE-MMS, ITE-CE [detail] | 2017-02-20 16:00 |
Hokkaido | Hokkaido Univ. | Speaker System with 100-W High Output Power and 0.17% THD+N Using 9-V Power Supply with Digitally Direct-Driven Technique Yuki Furuya, Masayoshi Takahashi, Satoshi Saikatsu, Akira Yasuda, Michitaka Yoshino (Hosei Univ.) |
In this paper, we report on a small speaker system that can output 110 W and higher from an 9-V input without using anal... [more] | |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Low-current, high-speed switched-capacitor amplifier with adaptive biasing technique Kazuki Takegawa, Tetsuya Hirose, Toshihiro Ozaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) ICD2016-87 CPSY2016-93 |
This paper proposes a switched-capacitor amplifier with adaptive biasing technique. The proposed amplifier employs adapt... [more] | ICD2016-87 CPSY2016-93 p.107 |
| EMCJ, IEE-EMC, MW, EST [detail] | 2016-10-20 11:20 |
Miyagi | Tohoku Univ. | An RF Frontend Amplifier Module for High SHF Wide-band Massive MIMO in 5G Keigo Nakatani, Shintaro Shinjo, Yuji Komatsuzaki, Jun Kamioka, Ryota Komaru, Hideyuki Nakamizo, Miyawaki Katsumi, Koji Yamanaka (Mitsubishi Electric) EMCJ2016-64 MW2016-96 EST2016-60 |
A highly integrated RF frontend module including a three-stage power amplifier (PA), a two-stage low noise amplifier (LN... [more] | EMCJ2016-64 MW2016-96 EST2016-60 pp.25-30 |
| MW (2nd) |
2016-06-09 - 2016-06-11 |
Overseas | KMUTNB, Bangkok, Thailand | An ultra-low-power RF-impulse transmitter with robustness to supply-voltage variation Takayoshi Obara, Yosuke Ishikawa, Sho Ikeda, Hiroyuki Ito, Noboru Ishihara, Shiro Dosho, Kazuya Masu (Tokyo Tech) |
This paper proposes an ultra-low-power RF-impulse transmitter for sensor networks. One of the conventional and low-power... [more] | |
| ICD | 2016-04-15 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
A 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with 0.07mJ/8kB Rewrite Energy and Endurance Over 100M Cycles Under Tj of 175°C Satoru Nakanishi, Hidenori Mitani, Ken Matsubara, Hiroshi Yoshida, Takashi Kono, Yasuhiko Taito, Takashi Ito, Takashi Kurafuji, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi (Renesas) ICD2016-15 |
A first-ever 90nm embedded 1T-MONOS Flash macro is presented to realize automotive reliability and simple process integr... [more] | ICD2016-15 pp.77-81 |
| ICD, CPSY | 2015-12-18 09:00 |
Kyoto | Kyoto Institute of Technology | Evaluation of Soft Error Tolerance of Redundant Flip-Flop in 65nm Bulk and FD-SOI Processes. Eiji Sonezaki, Kubota Kanto, Masaki Masuda, Shohei Kanda, Jun Furuta, Kazutoshi Kobayashi (KIT) ICD2015-83 CPSY2015-96 |
According to process down scaling, LSI becomes less reliable for soft errors. To increase the tolerance of FFs for soft ... [more] | ICD2015-83 CPSY2015-96 pp.69-74 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2015-57 DC2015-53 |
This paper describes a sleep control technique using leakage monitor circuit to implement Fine-Grain Power Gating (FGPG)... [more] | VLD2015-57 DC2015-53 pp.129-134 |
| SRW | 2015-08-24 15:40 |
Tokyo | Shibaura Institute of Technology | A study on the performance improvement of a synchronous power-saving wireless communication system by the clock drift correction Yasutaka Kawamoto, Toshihiko Matsunaga (OKI), Yuichi Kado (KIT) SRW2015-22 |
Sensor networks for infrastructure monitoring, it has to be able to long-term operation of about 10 years battery. Infra... [more] | SRW2015-22 pp.65-70 |
| SIS | 2015-06-08 13:00 |
Nagasaki | Arkas SASEBO | [Tutorial Lecture]
Power saving techniques for wireless communication systems using cross layer designs of OSI model Masayuki Kurosaki (Kyutech) SIS2015-1 |
In this tutorial, we explain an outline of low power consumption methods for wireless LAN systems based on cross layer d... [more] | SIS2015-1 pp.1-6 |
| VLD, IPSJ-SLDM | 2015-05-14 11:35 |
Fukuoka | Kitakyushu International Conference Center | Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-4 |
Recently, clock gating is utilized as a method for reducing the dynamic power of LSI. Clock gating can be automatically... [more] |
VLD2015-4 pp.31-36 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 09:20 |
Kagoshima | A Study on a Power Efficient Neurochip with Non-Volatile Memory Jun Tomii, Masaaki Kondo, Hiroshi Nakamura (Univ. Tokyo) CPSY2014-176 DC2014-102 |
Along with the evolution of machine learning techniques, neurochips, which are designed for fast neural network processi... [more] | CPSY2014-176 DC2014-102 pp.83-88 |
|
| RCS, SR, SRW (Joint) |
2015-03-04 09:50 |
Tokyo | Tokyo Institute of Technology | Cooperative sensing scheme weighted by estimated detection probability and its performance characteristics Tomoki Sada, Kanshiro Kashiki, Kosuke Yamazaki, Shingo Watanabe (KDDI R&D Labs) SR2014-113 |
The spectrum sharing schemes to use the same frequency spectrum by multiple radio communication systems are currently be... [more] | SR2014-113 pp.15-22 |
| OCS, CS (Joint) |
2015-01-22 15:35 |
Tokushima | Tokushima University | [Special Invited Talk]
Low-power Techniques for Network System on a Chip Satoshi Shigematsu, Naoki Miura, Yuki Arikawa, Namiko Ikeda (NTT) CS2014-83 |
This paper presents examples of low-power circuit schemes for Network SoC and lowering power of network equipment by usi... [more] | CS2014-83 pp.13-18 |
| MW (2nd) |
2014-11-26 - 2014-11-28 |
Overseas | King Mongkut's Institute of Technology Ladkrabang (KMITL), Bangkok | A 0.5-V 5.8-GHz Current-Reuse-VCO-Based PLL with Amplitude Regulation Technique Sho Ikeda, Sang_yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Tech.) |
This paper presents design and detail measurement results of the ultra-low-power 5.8-GHz PLL with a current-reuse VCO an... [more] | |
| ICD, ITE-IST | 2014-07-03 11:15 |
Shimane | Izumo-shi (Shimane) | [Invited Talk]
Extremely Low Power and Low Voltage Sucessive Approximation Register ADC Hiroki Ishikuro (Keio Univ.) ICD2014-22 |
Recently, large number of research results of energy efficient, charge redistribution type, successive approximation reg... [more] | ICD2014-22 pp.17-22 |
| VLD | 2014-03-05 14:15 |
Okinawa | Okinawa Seinen Kaikan | Post –Silicon Tuning of Body Biasing and Clock Skew for Low-Voltage LSI Tatsunori Kubo, Mineo Kaneko (JASIT) VLD2013-163 |
As the device feature size decreases, operation speed increases and supply voltage decreases, variation of the signal pr... [more] | VLD2013-163 pp.159-163 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 15:50 |
Kanagawa | Hiyoshi Campus, Keio University | A Case for Low-Power Networks using FSO and On/Off Links Tomoya Ozaki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) VLD2013-114 CPSY2013-85 RECONF2013-68 |
Power consumption of interconnection networks incrases as the scale of supercomputers and high-end datacenters increases... [more] | VLD2013-114 CPSY2013-85 RECONF2013-68 pp.73-78 |
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