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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD, ITE-IST [detail] | 2023-08-01 13:00 |
Hokkaido | Hokkaido Univ. Multimedia Education Bldg. 3F (Primary: On-site, Secondary: Online) |
[Invited Talk]
R and D of Low Power Semiconductor Technology and It's Application Expansions
-- Review R and D of Semiconductor device and LSI for these 43 years -- Koichiro Ishibashi (UEC)  SDM2023-38 ICD2023-17 |
LSI density has been doubling every two years for 64 years, since Moore’s law started in 1959. The presenter began resea... [more] | SDM2023-38 ICD2023-17 pp.14-15 |
| HWS, VLD | 2023-03-02 09:55 |
Okinawa | (Primary: On-site, Secondary: Online) |
Implementation of power-outage tolerant VLSI system using asynchronous circuits Masashi Imai (Hirosaki Univ.) VLD2022-86 HWS2022-57 |
Re-initialization free systems which contain nonvolatile memory have been proposed in order to cope with power-outage. H... [more] | VLD2022-86 HWS2022-57 pp.79-84 |
| HWS, VLD | 2023-03-03 09:55 |
Okinawa | (Primary: On-site, Secondary: Online) |
Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat) VLD2022-101 HWS2022-72 |
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] | VLD2022-101 HWS2022-72 pp.149-154 |
| CAS, SIP, VLD, MSS | 2022-06-17 10:00 |
Aomori | Hachinohe Institute of Technology (Primary: On-site, Secondary: Online) |
[Panel Discussion]
Contributions of System and Signal Processing Subsociety to the SDGs Shigemasa Takai (Osaka Univ.), Yoshinobu Maeda (Niigata Univ.), Namiko Ikeda (NTT), Toshihisa Tanaka (TUAT), Atsuo Ozaki (OIT) CAS2022-11 VLD2022-11 SIP2022-42 MSS2022-11 |
The four technical committees (TCs) on Systems and Signal Processing subsociety, i.e., TCs of Circuits and Systems (CA... [more] |
CAS2022-11 VLD2022-11 SIP2022-42 MSS2022-11 pp.58-60 |
| VLD, HWS [detail] | 2022-03-07 09:35 |
Online | Online | Bottleneck Channel Routing to Reduce the Area of Analog VLSI Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat) VLD2021-77 HWS2021-54 |
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] | VLD2021-77 HWS2021-54 pp.7-12 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 14:45 |
Online | Online | Diagnosis of Switching-Induced IR Drop by On-Chip Voltage Monitors Kazuki (Kobe Univ.), Leonidas Kataselas (Aristotle Univ.), Ferenc Fodor (IMEC), Alkis Hatzopoulos (Aristotle Univ.), Makoto Nagata (Kobe Univ.), Erik Jan Marinissen (IMEC) VLD2021-31 ICD2021-41 DC2021-37 RECONF2021-39 |
On-chip monitor (OCM) circuits enable us to observe dynamic power-supply (PS) waveforms within power domains individuall... [more] | VLD2021-31 ICD2021-41 DC2021-37 RECONF2021-39 pp.83-86 |
| SIP, CAS, VLD, MSS | 2021-07-05 13:30 |
Online | Online | [Panel Discussion]
[Panel Discussion] The Role of System and Signal Processing Subsociety
-- Challenge to IoT (Internet of Things) issues -- Hideaki Okazaki (SIT), Hiroki Sato (SONY), Kazutoshi Kobayashi (KIT), Atsuo Ozaki (OIT), Kazunori Hayashi (KU), Toshihisa Tanaka (TUAT) CAS2021-4 VLD2021-4 SIP2021-14 MSS2021-4 |
The four technical committees (TCs) of Systems and Signal Processing sub-society, i.e., TCs of Circuits and Systems (CA... [more] |
CAS2021-4 VLD2021-4 SIP2021-14 MSS2021-4 pp.16-18 |
| MSS, CAS, SIP, VLD | 2020-06-18 15:00 |
Online | Online | [Panel Discussion]
The role of System and Signal Processing Subsociety
-- Pros & Cons of Online Video Meeting -- Shogo Muramatsu (Niigata Univ.), Shigemasa Takai (Osaka Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Kasunori Hayashi (Kyoto Univ.), Daisuke Fukuda (Fujitsu Lab.) CAS2020-10 VLD2020-10 SIP2020-26 MSS2020-10 |
The four technical committees (TCs) of Systems and Signal Processing sub-society, i.e., TCs of Circuits and Systems (CAS... [more] | CAS2020-10 VLD2020-10 SIP2020-26 MSS2020-10 pp.53-56 |
| HWS, VLD | 2019-02-27 15:45 |
Okinawa | Okinawa Ken Seinen Kaikan | Timing Correction by Constrained Temperature Dependent Clock Skew Mineo Kaneko (JAIST) VLD2018-103 HWS2018-66 |
This report treats temperature dependent clock skew scheduling for a general class of sequential circuits. Previous stud... [more] | VLD2018-103 HWS2018-66 pp.61-66 |
| CAS, SIP, MSS, VLD | 2018-06-15 12:25 |
Hokkaido | Hokkaido Univ. (Frontier Research in Applied Sciences Build.) | [Panel Discussion]
The role of System and Signal Processing Subsociety
-- The roadmaps of groups and subsociety Part 1 -- Satoshi Yamane (Kanazawa Univ.), Hideaki Okazaki (Shonan Inst. of Tech.), Noriyuki Minegishi (Mitsubishi Electric), Shogo Muramatsu (Niigata Univ.), Morikazu Nakamura (Univ. of the Ryukyus) CAS2018-25 VLD2018-28 SIP2018-45 MSS2018-25 |
The four technical committees CAS, VLD, SIP, and MSS of System and Signal Processing Subsociety holds joint workshop sin... [more] | CAS2018-25 VLD2018-28 SIP2018-45 MSS2018-25 p.129 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas Electronics) VLD2017-36 DC2017-42 |
Today, semiconductor technologies have developed and advance the integration density of LSI circuits. A technique which... [more] |
VLD2017-36 DC2017-42 pp.55-60 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:25 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | On Avoiding Test Data Corruption by Optimal Scan Chain Grouping Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara (KIT), Jun Qian (AMD) VLD2017-42 DC2017-48 |
Scan shift operations cause many gates to switch simultaneously. As a result, excessive IR-drop may occur, disrupting th... [more] | VLD2017-42 DC2017-48 pp.91-94 |
| VLD | 2017-03-03 09:00 |
Okinawa | Okinawa Seinen Kaikan | Dynamic Power Optimization for Asynchronous Circuits with Bundled-data Implementation based on the Mobility of Operations Shunya Hosaka, Hiroshi Saito (Aizu Univ) VLD2016-122 |
In this paper, we propose a dynamic power optimization for asynchronous circuits with bundled-data implementation based ... [more] | VLD2016-122 pp.109-114 |
| DC | 2017-02-21 12:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design) DC2016-77 |
Today, advancements of semiconductor technology have progress to high integration of LSI circuits. A technique which ke... [more] |
DC2016-77 pp.17-22 |
| DC | 2016-06-20 14:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Relationship between the Number of Fan-Outs and Its Wire-length for a logic gate Taiki Kobayashi, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.) DC2016-12 |
Many analysis and algorithms have been proposed to reduce wire-lengths based on Steiner trees for VLSI layout designs. A... [more] | DC2016-12 pp.13-18 |
| VLD, CAS, MSS, SIP | 2016-06-16 13:20 |
Aomori | Hirosaki Shiritsu Kanko-kan | [Panel Discussion]
The Role of System and Signal Processing Subsociety
-- Encouragement and Development of Young Researchers -- Yoshinobu Kajikawa (Kansai Univ.), Shunsuke Koshita (Tohoku Univ.), Takashi Takenaka (NEC), Yuichi Tanaka (TUAT), Satoshi Yamane (Kanazawa Univ.) CAS2016-9 VLD2016-15 SIP2016-43 MSS2016-9 |
The four technical committees of System and Signal Processing Subsociety have been holding joint workshop since 2010. We... [more] | CAS2016-9 VLD2016-15 SIP2016-43 MSS2016-9 p.47 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-67 DC2015-63 |
In synchronous circuits, it is needed to distribute an identical clock signal to the whole chip with a constant frequenc... [more] | VLD2015-67 DC2015-63 pp.189-194 |
| MSS, CAS, SIP, VLD | 2015-06-17 16:20 |
Hokkaido | Otaru University of Commerce | [Panel Discussion]
The Role of System and Signal Processing Subsociety
-- Society Activity and Job Search -- Atsushi Takahashi (Tokyo Tech), Yoshihiro Kaneko (Gifu Univ.), Yusuke Matsunaga (Kyushu Univ.), Osamu Hoshuyama, Yuichi Nakamura (NEC) CAS2015-12 VLD2015-19 SIP2015-43 MSS2015-12 |
The four technical committees of System and Signal Processing Subsociety have been holding joint workshop since 2010. We... [more] | CAS2015-12 VLD2015-19 SIP2015-43 MSS2015-12 p.65 |
| VLD, IPSJ-SLDM | 2015-05-14 11:35 |
Fukuoka | Kitakyushu International Conference Center | Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-4 |
Recently, clock gating is utilized as a method for reducing the dynamic power of LSI. Clock gating can be automatically... [more] |
VLD2015-4 pp.31-36 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 17:40 |
Kanagawa | Hiyoshi Campus, Keio University | Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits Toshihiro Takeshita, Shinichi Nishizawa, AKM Mahfuzul Islam, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ) VLD2014-129 CPSY2014-138 RECONF2014-62 |
Simultaneous supply and threshold voltage tuning has a strong impact on the energy reduction of LSI circuits. Therefore,... [more] | VLD2014-129 CPSY2014-138 RECONF2014-62 pp.111-116 |
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