|
|
All Technical Committee Conferences (Searched in: All Years)
|
|
Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
|
Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SCE |
2019-04-19 09:55 |
Tokyo |
|
Demonstration of an SFQ/CMOS hybrid memory system using a one-instruction-set SFQ microprocessor Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2019-2 |
SFQ/CMOS hybrid system, which is a hybridized system of SFQ circuits and CMOS memories, has been proposed as a large-sca... [more] |
SCE2019-2 pp.7-11 |
MSS, CAS, SIP, VLD |
2015-06-17 10:45 |
Hokkaido |
Otaru University of Commerce |
Extension of One-Instruction-Set Computer and Its Evaluation Noriaki Sakamoto, Tanvir Ahmed (Tokyo Tech), Jason H. Anderson (Univ. of Toronto), Yuko Hara-Azumi (Tokyo Tech) CAS2015-4 VLD2015-11 SIP2015-35 MSS2015-4 |
Subleq computer is one of the best-known Turing-Complete One-Instruction-Set Computers. Subleq instruction is a three-op... [more] |
CAS2015-4 VLD2015-11 SIP2015-35 MSS2015-4 pp.19-24 |
|
|
|
Copyright and reproduction :
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
|
[Return to Top Page]
[Return to IEICE Web Page]
|