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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF, CPSY, VLD, IPSJ-SLDM [detail] |
2015-01-30 09:30 |
Kanagawa |
Hiyoshi Campus, Keio University |
Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D Katsuki Kyan, Makoto Arakaki, Yusuke Hirai, Hiroki Nakasone (Univ. of the Ryukyus), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.), Yasunori Osana (Univ. of the Ryukyus) VLD2014-134 CPSY2014-143 RECONF2014-67 |
FLOPS-2D is a multiple-FPGA computer system that consists of several FLOPS boards. Each FLOPS board has one FPGA, memory... [more] |
VLD2014-134 CPSY2014-143 RECONF2014-67 pp.139-143 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:00 |
Oita |
B-ConPlaza |
Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator Takashi Okamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-42 |
The circuit scale of Application Specific Integrated Circuit(ASIC)has been increasing. Therefore the shortening of funct... [more] |
RECONF2014-42 pp.45-50 |
RECONF |
2013-05-21 10:10 |
Kochi |
Kochi Prefectural Culture Hall |
Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-10 |
Recently, development period of ASIC is longer becouse of the increase in circuit scale.
Verification process accounts ... [more] |
RECONF2013-10 pp.49-54 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:25 |
Fukuoka |
Kitakyushu International Conference Center |
FTN Simulation Technology Based on Analysis of Frequency, Time and Noise for High-speed Serial Communication System Goichi Ono, Takashi Takemoto, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi) CPSY2007-38 |
We introduce a FTN simulation technology and its circuit behavior models for a high-speed serial communication system be... [more] |
CPSY2007-38 pp.19-24 |
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 16:50 |
Fukuoka |
Kitakyushu International Conference Center |
The Evaluation of High-speed Serial Communication System by Using FTN Simulation Technology Takashi Takemoto, Goichi Ono, Koji Fukuda, Fumio Yuki, Ryo Nemoto, Eiichi Suzuki, Masayoshi Yagyu, Hiroki Yamashita, Tatsuya Saito (Hitachi) CPSY2007-39 |
We describe a FTN simulation technology for high-speed serial interface which is high-accuracy behavior model based on a... [more] |
CPSY2007-39 pp.25-30 |
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