Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] |
2021-01-26 13:10 |
Online |
Online |
Automated architecture exploration on Scala-based hardware development environment Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) VLD2020-62 CPSY2020-45 RECONF2020-81 |
In recent years, reconfigurable architectures such as FPGAs have been attracting more and more attention.
Design Space... [more] |
VLD2020-62 CPSY2020-45 RECONF2020-81 pp.131-136 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2020-02-27 17:00 |
Kagoshima |
Yoron-cho Chuou-Kouminkan |
HLS by multi-objective optimization under resource constraints
-- Approach to extracting coarse-grained parallelism using functional language -- Fukuhei Hamazaki, Tetsuro Yamazaki, Ryota Shioya (U-Tokyo), Kenichi Koizumi, Hiroshi Tezuka, Mary Inaba (U-Tokyo) CPSY2019-104 DC2019-110 |
For engineers who are not familiar with circuits, it is difficult to optimize circuit considering trade-off factors such... [more] |
CPSY2019-104 DC2019-110 pp.99-104 |
ICTSSL, CAS |
2020-01-30 18:00 |
Tokyo |
|
High-level synthesis oriented histogram series duplication for overlapping continuous image processing Moena Yamasaki, Akira Yamawaki (Kyutech) CAS2019-80 ICTSSL2019-49 |
In order to quickly realize a high-performance and power-saving embedded image processing device, it is effective to use... [more] |
CAS2019-80 ICTSSL2019-49 pp.85-89 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2020-01-23 11:50 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Binary Synthesis from RISC-V Executables Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-71 CPSY2019-69 RECONF2019-61 |
This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction s... [more] |
VLD2019-71 CPSY2019-69 RECONF2019-61 pp.111-115 |
RECONF |
2019-09-20 10:40 |
Fukuoka |
KITAKYUSHU Convention Center |
Multi-threaded High-Level Synthesis for Bandwidth-intensive Applications Jens Huthmann, Auter Podobas, Takaaki Miyajima, Atsushi Koshiba, Kentaro Sano (RIKEN) RECONF2019-30 |
Using stream computing on Field-Programmable Gate Arrays (FPGAs) has in the recent decades shown promise for practical ... [more] |
RECONF2019-30 pp.51-56 |
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] |
2019-07-24 13:45 |
Kochi |
Kochi University of Technology |
Design Space Search Applying Bayesian Optimization to High-level Design Flow Ryohei Nakayama (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 |
Now that circuit scale is increasing, high-level synthesis technology that designs circuits using high-level programming... [more] |
ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 pp.369-374 |
HWS, VLD |
2019-03-01 10:00 |
Okinawa |
Okinawa Ken Seinen Kaikan |
Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85 |
This paper presents a method of automatically synthesizing a hardware
design from a set of source codes for a real-time... [more] |
VLD2018-122 HWS2018-85 pp.175-180 |
HWS, VLD |
2019-03-01 11:15 |
Okinawa |
Okinawa Ken Seinen Kaikan |
Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs Sayuri Ota, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2018-125 HWS2018-88 |
This article presents a method for synthesizing circuits with distributed control from CDFGs (control data flow graphs).... [more] |
VLD2018-125 HWS2018-88 pp.193-198 |
VLD, HWS (Joint) |
2018-02-28 14:20 |
Okinawa |
Okinawa Seinen Kaikan |
Development of Loop Flattening Tool that Reduces Cycle Overhead in Loop Pipelining of Nested Loops in High Level Synthesis Daisuke Ishikawa, Kenshu Seto (TCU) VLD2017-97 |
We develop a loop flattening tool for designing hardware with high level synthesis. When loop pipelining is applied to ... [more] |
VLD2017-97 pp.49-54 |
VLD, HWS (Joint) |
2018-02-28 16:55 |
Okinawa |
Okinawa Seinen Kaikan |
Reliability Evaluation of Mixed Error Correction Scheme for Soft-Error Tolerant Datapaths Junghoon Oh, Mineo Kaneko (JAIST) VLD2017-102 |
Among several problems with miniaturization of LSIs, soft-errors are one of serious problems to make reliability worse. ... [more] |
VLD2017-102 pp.79-84 |
VLD, HWS (Joint) |
2018-03-01 16:25 |
Okinawa |
Okinawa Seinen Kaikan |
A Concept of DNN Framework for Embedded System Using FPGA Ryota Yamamoto, Takuya Okamoto, Shinya Honda (Nagoya Univ.), Qian Zhao, Toki Matsumoto, Yukikazu Nakamoto (Hyogo Univ.), Tamotsu Sakai, Tetsuya Aoyama, Kazutoshi Wakabayashi (NEC) VLD2017-117 |
Recently, a DNN (Deep Neural Network) is used in many areas, and it required a field of an embedded system.
For an em... [more] |
VLD2017-117 pp.169-174 |
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] |
2018-01-18 17:00 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University |
Distributed Memory Architecture for High-Level Synthesis from Erlang Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2017-75 CPSY2017-119 RECONF2017-63 |
This paper presents a distributed memory architecture for dedicated
hardware automatically synthesized from Erlang prog... [more] |
VLD2017-75 CPSY2017-119 RECONF2017-63 pp.77-82 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 10:55 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) VLD2017-28 DC2017-34 |
A three-dimensional (3D) sound processor architecture that includes 3D sound processing intellectual property (IP) cores... [more] |
VLD2017-28 DC2017-34 pp.7-12 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 10:30 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table Yuji Shindo, Kenshu Seto, Hao San (TCU) VLD2017-44 DC2017-50 |
We propose an area reduction method of digital circuit part in analog-to-digital converter (ADC) based on β-expansion. T... [more] |
VLD2017-44 DC2017-50 pp.101-104 |
RECONF |
2017-09-26 13:55 |
Tokyo |
DWANGO Co., Ltd. |
A case study of High-level Synthesis Using Higher-order Function on Functional Language Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2017-35 |
The growing capabilities of silicon technology and the increasing complexity of applications in recent decades have forc... [more] |
RECONF2017-35 pp.75-80 |
VLD, IPSJ-SLDM |
2017-05-10 13:30 |
Fukuoka |
Kitakyushu International Conference Center |
VLD2017-1 |
In this paper, we present techniques to automatically generate high-level C description after ECO (Engineering Change Or... [more] |
VLD2017-1 pp.1-6 |
VLD |
2017-03-01 15:55 |
Okinawa |
Okinawa Seinen Kaikan |
A Design Technique for Approximate Circuits based on Artificial Neural Network Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-106 |
This paper proposes a design technique for approximate circuits based on artificial neural network, and then evaluates t... [more] |
VLD2016-106 pp.25-30 |
VLD |
2017-03-02 15:00 |
Okinawa |
Okinawa Seinen Kaikan |
Resource Binding and Domain Assignment for Multi-Domain Clock Skew Aware High-Level Synthesis Xiaoguang Li, Mineo Kaneko (JAIST) VLD2016-118 |
The performance of data path circuit can be improved by shifting the clock signal arrival time intentionally. In order t... [more] |
VLD2016-118 pp.85-90 |
VLD |
2017-03-02 15:50 |
Okinawa |
Okinawa Seinen Kaikan |
MILP Approach to Skew-Aware High Level Synthesis Kai Shimura, Mineo Kaneko (JAIST) VLD2016-120 |
Intentional clock skew is known as one of the promising techniques for enhancing the circuit speed.
However, when we tr... [more] |
VLD2016-120 pp.97-102 |
VLD |
2017-03-03 13:25 |
Okinawa |
Okinawa Seinen Kaikan |
Effect on the Chip Area of Component Adjacency Constraint for Soft-Error Tolerant Datapaths Junghoon Oh, Mineo Kaneko (JAIST) VLD2016-129 |
Due to the downsizing of VLSI, reliability issues caused by soft-errors have become more explicit. Several studies in sy... [more] |
VLD2016-129 pp.151-156 |