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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IT, RCS, SIP | 2023-01-24 10:00 |
Gunma | Maebashi Terrsa (Primary: On-site, Secondary: Online) |
A hierarchical construction of typical linear codes Kaito Suzuki, Tomohiko Uyematsu (Tokyo Tech.)  IT2022-35 SIP2022-86 RCS2022-214 |
According to Shannon's channel coding theorem, a channel has an inherent amount called a channel capacity which is deter... [more] | IT2022-35 SIP2022-86 RCS2022-214 pp.36-41 |
| AI | 2018-08-27 14:15 |
Osaka | Temporal Variability of Precipitation Events in Fukuoka, Kumamoto, and Kagoshima in Kyusyu Naoki Matsumoto, Kenta Ogino (Kumamoto Univ.), Ken-ichi Fukui (Osaka Univ.), Tomohiko Tomita (Kumamoto Univ.) AI2018-20 |
This work quantitatively evaluates the differences in rainfall events in Fukuoka, Kumamoto, and Kagoshima, which are lo... [more] | AI2018-20 pp.39-44 |
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| ICD | 2017-04-20 11:00 |
Tokyo | [Invited Talk]
A 4Gb LPDDR2 STT-MRAM with Compact 9F2 1T1MTJ Cell and Hierarchical Bitline Architecture Kenji Tsuchida (Toshiba), Kwangmyoung Rho, Dongkeun Kim (SK hynix), Yutaka Shirai (Toshiba), Jihyae Bae (SK hynix), Tsuneo Inaba, Hiromi Noro (Toshiba), Hyunin Moon, Sungwoong Chung (SK hynix), Kazumasa Sunouchi (Toshiba), Jinwon Park, Kiseon Park (SK hynix), Akihito Yamamoto (Toshiba), Seoungju Chung, Hyeongon Kim (SK hynix) ICD2017-3 |
The experimental 4-Gbit STT-MRAM with 9F2 1T1MTJ cell of 90nm by 90nm is presented. Hierarchical bit line architecture a... [more] | ICD2017-3 pp.11-16 |
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| ICD | 2013-04-12 14:45 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
A 13.8pJ/Access/Mbit SRAM with Charge Collector Circuits for Effective Use of Non-Selected Bit Line Charges Shinichi Moriwaki, Yasue Yamamoto, Toshikazu Suzuki (STARC), Atsushi Kawasumi (Toshiba), Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. Tokyo) ICD2013-20 |
1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm t... [more] | ICD2013-20 pp.103-108 |
| IBISML | 2013-03-05 15:40 |
Aichi | Nagoya Institute of Technology | Hierarchical Multi-label Classification on Statistical Decision Theory Kiyohito Yamamoto, Tota Suko, Toshiyasu Matsushima (Waseda Univ.) IBISML2012-107 |
This paper considers multi-label classification on statistical decision theory. In Label Power Set format, multi-label c... [more] | IBISML2012-107 pp.101-106 |
| ICD | 2010-04-22 15:45 |
Kanagawa | Shonan Institute of Tech. | A 32-Mb SPRAM with localized bi-directional write driver, '1'/'0' dual-array equalized reference scheme, and 2T1R memory cell layout Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi (Hitachi), Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2010-10 |
A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ... [more] | ICD2010-10 pp.53-57 |
| ICD, SDM | 2007-08-24 16:05 |
Hokkaido | Kitami Institute of Technology | A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial) SDM2007-168 ICD2007-96 |
We propose a new 2port SRAM with a 8T single-read-bitline (SRBL) memory cell for 45nm SOCs. Access time tends to be slow... [more] | SDM2007-168 ICD2007-96 pp.145-148 |
| ICD | 2005-04-15 13:00 |
Fukuoka | A 1.5-ns Access-Time 0.25-μm CMOS/SIMOX SRAM Macrocell
-- High Speed and Low-Power Operation by Using Dual-Wordline Scheme -- Nobutaro Shibata, Takako Ishihara (NTT), Shigehiro Kurita, Hideomi Okiyama (NEL) |
This paper presents high speed and low-power circuit techniques for small size SRAMs (e.g., on-chip cache memories). Rea... [more] | ICD2005-16 pp.19-24 |
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