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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NLP, MICT, MBE, NC (Joint) [detail] |
2022-01-23 09:50 |
Online | Online | Analog-circuit design of STDP learning rule with linear decay and its LSI implementation Satoshi Moriya, Tatsuki Kato (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Hideaki Yamamoto, Shigeo Sato, Yoshihiko Horio (Tohoku Univ.)  NC2021-40 |
Spiking neural networks (SNNs) are expected to be the next generation of information processing technology to reduce the... [more] | NC2021-40 p.44 |
| HWS, VLD [detail] | 2021-03-03 14:55 |
Online | Online | Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
| HWS, VLD [detail] | 2021-03-04 13:25 |
Online | Online | A Low-Latency Memory Encryption Scheme with Tweakable Block Cipher and Its Hardware Design Maya Oda, Rei Ueno, Naofumi Homma (Tohoku Univ.), Akiko Inoue, Kazuhiko Minematsu (NEC) VLD2020-83 HWS2020-58 |
In this paper, we propose a highly efficient memory protection method based on the Tweakable block cipher (TBC). The lat... [more] | VLD2020-83 HWS2020-58 pp.85-90 |
| HWS, VLD [detail] | 2021-03-04 13:50 |
Online | Online | Design and Evaluation of Efficient AES S-box Hardware with Optimization of Linear Mappings Ayano Nakashima, Rei Ueno, Naofumi Homma (Tohoku Univ.) VLD2020-84 HWS2020-59 |
This paper presents a new AES S-Box hardware design based on the optimization of linear mappings by combining multiplica... [more] | VLD2020-84 HWS2020-59 pp.91-96 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 14:50 |
Online | Online | Efficient Attention Mechanism by Softmax Function with Trained Coefficient Kaito Hirota (UT), O'uchi Shinichi (AIST), Fujita Masahiro (UT) VLD2020-48 CPSY2020-31 RECONF2020-67 |
BERT is a neural network model which has accomplished state-of-the-art performance on eleven natural language processing... [more] | VLD2020-48 CPSY2020-31 RECONF2020-67 pp.52-57 |
| ICD, HWS [detail] | 2020-10-26 13:00 |
Online | Online | Design of Efficient AES Hardware with Immediately Fault Detection Capability Yusuke Yagyu, Rei Ueno, Naofumi Homma (Tohoku Univ.) HWS2020-31 ICD2020-20 |
This paper presents an efficient AES encryption/decryption hardware architecture with a fault detection scheme. The pr... [more] |
HWS2020-31 ICD2020-20 pp.36-41 |
| ICD, HWS [detail] | 2020-10-26 14:55 |
Online | Online | Physical-Level Detection Approach against Hardware Trojans inside Semiconductor Chips (II) Hirofumi Sakane, Shinichi Kawamura, Kentaro Imafuku, Yohei Hori, Makoto Nagata, Yuichi Hayashi, Tsutomu Matsumoto (AIST) HWS2020-35 ICD2020-24 |
Hardware Trojans, known to be designed and crafted with malicious intent and deployed to be part of the hardware of the ... [more] | HWS2020-35 ICD2020-24 pp.59-64 |
| ICD, HWS [detail] | 2020-10-26 15:45 |
Online | Online | Low-Latency Countermeasure Circuit Oriented Hardware Trojan and its Evaluation Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) HWS2020-37 ICD2020-26 |
Outsourcing and the use of IP are the mainstream in the design and manufacturing of system LSIs. On the other hand, the ... [more] | HWS2020-37 ICD2020-26 pp.71-76 |
| ICD, HWS [detail] | 2020-10-26 17:40 |
Online | Online | Investigation of High-Efficiency Simulation Method for Detection of Physical Design Falsification in Secure IC Chip Kazuki Yasuda, Kazuki Monta, Daichi Nakagawa, Makoto Nagata (Kobe Univ.) HWS2020-41 ICD2020-30 |
With the development of the IoT society in recent years, various security measures have been developed for integrated ci... [more] | HWS2020-41 ICD2020-30 pp.94-98 |
| HWS, VLD [detail] | 2020-03-05 10:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Motor Current Signature Analysis Based On-Line Fault Detection of DC Motor Naoki Osako (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM), Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-111 HWS2019-84 |
This article presents a method for online detection of DC motors' fault based on current signature analysis. While cu... [more] |
VLD2019-111 HWS2019-84 pp.101-106 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-23 11:50 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Binary Synthesis from RISC-V Executables Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-71 CPSY2019-69 RECONF2019-61 |
This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction s... [more] | VLD2019-71 CPSY2019-69 RECONF2019-61 pp.111-115 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 10:45 |
Ehime | Ehime Prefecture Gender Equality Center | VLD2019-38 ICD2019-28 IE2019-34 CPSY2019-41 DC2019-62 RECONF2019-39 |
Introducing AI technology trends that have been attracting attention in recent years and an overview of deep learning, w... [more] | VLD2019-38 ICD2019-28 IE2019-34 CPSY2019-41 DC2019-62 RECONF2019-39 pp.93-94(VLD), pp.3-4(ICD), pp.3-4(IE), pp.3-4(CPSY), pp.93-94(DC), pp.21-22(RECONF) |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:35 |
Ehime | Ehime Prefecture Gender Equality Center | Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths Suguru Rikino, Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.) VLD2019-46 DC2019-70 |
Hardware Trojan detection is important to ensure security of LSIs. If a hardware Trojan is inserted in a signal line o... [more] |
VLD2019-46 DC2019-70 pp.151-155 |
| HWS, ICD [detail] | 2019-11-01 14:15 |
Osaka | DNP Namba SS Bld. | A Design of Isogeny-Based Cryptographic Hardware Architecture Using Residue Number System Shuto Funakoshi, Rei Ueno, Naofumi Homma (Tohoku Univ.) HWS2019-60 ICD2019-21 |
In this paper, we will propose an efficient hardware architecture of isogeny-based cryptography. The proposed architectu... [more] | HWS2019-60 ICD2019-21 pp.19-24 |
| HWS, ICD [detail] | 2019-11-01 16:00 |
Osaka | DNP Namba SS Bld. | A Study of Hardware Trojan Detection Method using Deep Learning in Asynchronous Circuits Hikaru Inafune, Masashi Imai (Hirosaki Univ.) HWS2019-63 ICD2019-24 |
There are typically two timing methods in VLSI designs known as synchronous circuits which use a global clock and async... [more] |
HWS2019-63 ICD2019-24 pp.35-40 |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-24 14:10 |
Kochi | Kochi University of Technology | Design of Highly Efficient AES Hardware Architectures Based on Multiplicative-Offset Rei Ueno (Tohoku Univ.), Sumio Morioka (IST), Noriyuki Miura, Kohei Matsuda, Makoto Nagata (Kobe Univ.), Shivam Bhasin (NTU), Yves Mathieu, Tarik Graba, Jean-Luc Danger (TPT), Naofumi Homma (Tohoku Univ.) ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61 |
This paper presents high throughput/gate hardware architectures. In order to achieve a high area-time efficiency, the pr... [more] | ISEC2019-58 SITE2019-52 BioX2019-50 HWS2019-53 ICSS2019-56 EMM2019-61 pp.375-382 |
| MBE | 2019-05-19 09:25 |
Niigata | Niigata University | A group-theoretic consideration on symmetry and redundancy of quadruped locomotion Yoshinobu Maeda, Mamoru Iwaki (Niigata Univ.) MBE2019-2 |
The Golubitsky-Buono theory based on mathematical group and symmetry is available to estimate a hardware design of CPG (... [more] | MBE2019-2 pp.7-12 |
| HWS | 2019-04-12 14:20 |
Miyagi | Tohoku University | Design of Unified Hardware Architecture for GF-Arithmetic Authenticated Encryption Schemes Shotaro Sawataishi, Rei Ueno, Naofumi Homma (Tohoku Univ.) HWS2019-3 |
This paper presents an efficient unified hardware for several authenticated encryption schemes based on Galois-field (GF... [more] | HWS2019-3 pp.13-18 |
| HWS, VLD | 2019-03-01 10:00 |
Okinawa | Okinawa Ken Seinen Kaikan | Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85 |
This paper presents a method of automatically synthesizing a hardware design from a set of source codes for a real-time... [more] |
VLD2018-122 HWS2018-85 pp.175-180 |
| HWS, VLD | 2019-03-02 10:00 |
Okinawa | Okinawa Ken Seinen Kaikan | An ultra-light weight implementation of PRINCE-family cryptographic processor Kohei Matsuda, Makoto Nagata, Noriyuki Miura (Kobe Univ.) VLD2018-137 HWS2018-100 |
An ultra-light-weight PRINCE cryptographic processor was proposed by Miura, et al. in 2017. In this paper, based on thi... [more] |
VLD2018-137 HWS2018-100 pp.261-265 |
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