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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS | 2024-04-19 16:25 |
Tokyo | (Primary: On-site, Secondary: Online) |
Non-Destructive Hardware Trojan Inspection by Backside Near Infrared Imaging Junichi Sakamoto, Yohei Hori, Shinichi Kawamura (AIST), Yuichi Hayashi (NAIST), Makoto Nagata (KU)  HWS2024-5 |
Hardware Trojan detection is a critical topic for maintaining the security of IC supply chain. Previous studies have rep... [more] | HWS2024-5 pp.18-23 |
| HWS | 2024-04-19 17:15 |
Tokyo | (Primary: On-site, Secondary: Online) |
Supply chain security of semiconductor chips and countermeasure design technologies Makoto Nagata (Kobe Univ.), Kazuki Monta (Secafy Co., Ltd.), Yuichi Hayashi (NAIST), Naofumi Homma (Tohoku Univ.) HWS2024-7 |
This report is dedicated to the threats and countermeasures of semiconductor supply chain security, regarding the authen... [more] | HWS2024-7 pp.30-33 |
| VLD, HWS, ICD | 2024-02-29 11:15 |
Okinawa | (Primary: On-site, Secondary: Online) |
Design of RISC-V SoC with Post-quantum Encryption Algorithm Acceleration Jiyuan Xin, Makoto Ikeda (UTokyo) VLD2023-110 HWS2023-70 ICD2023-99 |
The foundational elements of the Internet of Things (IoT) are increasingly intricate and robust Systems-on-Chips (SoCs) ... [more] | VLD2023-110 HWS2023-70 ICD2023-99 pp.66-71 |
| VLD, HWS, ICD | 2024-03-01 15:30 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Pipelined NTT Transformer and its Extension Scheme Designed for the Digital Signature Scheme Crystals-Dilithium Pengfei Sun, Makoto Ikeda (Tokyo Univ.) VLD2023-130 HWS2023-90 ICD2023-119 |
As quantum computing advances, it threatens the security of current encryption algorithms, making Post-Quantum Cryptogra... [more] | VLD2023-130 HWS2023-90 ICD2023-119 pp.161-166 |
| VLD, HWS, ICD | 2024-03-01 16:20 |
Okinawa | (Primary: On-site, Secondary: Online) |
An Efficient Hardware Approach for High-Speed SPHINCS+ Signature Generation Yuta Takeshima, Makoto Ikeda (The Univ. of Tokyo) VLD2023-132 HWS2023-92 ICD2023-121 |
This study addresses the challenges traditional cryptographic systems face with the advent of quantum computers by focus... [more] | VLD2023-132 HWS2023-92 ICD2023-121 pp.173-177 |
| VLD, HWS, ICD | 2024-03-02 10:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Design of General Hardware for Optimal Strategy in Isogeny-Based Post-Quantum Cryptography Kosei Nakamura, Makoto Ikeda (UT) VLD2023-137 HWS2023-97 ICD2023-126 |
The computation in isogeny-based post-quantum cryptography primarily consists of two operations: scalar multiplication o... [more] | VLD2023-137 HWS2023-97 ICD2023-126 pp.198-203 |
| RECONF, VLD | 2024-01-30 13:20 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2023-94 RECONF2023-97 |
This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path... [more] | VLD2023-94 RECONF2023-97 pp.81-86 |
| RECONF, VLD | 2024-01-30 14:50 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
FPGA-Accelerated Random Forest for Real-Time IoT Intrusion Detection Qingyu Zeng, Yuko Hara (Tokyo Tech) VLD2023-97 RECONF2023-100 |
The rapid proliferation of the Internet of Things (IoT) has heightened cyber security concerns, necessitating efficient ... [more] | VLD2023-97 RECONF2023-100 pp.99-104 |
| QIT (2nd) |
2023-12-17 17:30 |
Okinawa | OIST (Primary: On-site, Secondary: Online) |
[Poster Presentation]
Assessing the PLGC Ansatz Performance in Noisy Quantum Settings: A Focus on the Toric Code [Poster presentation] Yaswitha Gujju (Univ. of Tokyo), Rong-Yang Sun, Tomonori Shirakawa, Seiji Yunoki (riken) |
In recent years, topologically ordered states have piqued interest due to their unique properties and potential applica... [more] |
|
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 13:45 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
VLD2023-50 ICD2023-58 DC2023-57 RECONF2023-53 |
In stochastic computing, which is a computational method with probabilities, various one-input functions, such as absolu... [more] | VLD2023-50 ICD2023-58 DC2023-57 RECONF2023-53 pp.106-111 |
| RECONF | 2023-09-15 13:50 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Abstraction of Processor-FPGA Communication in Reconfigurable Virtual Accelerator (ReVA) Eriko Maeda, Kazuki Yaguchi, Shunya Kawai, Daichi Teruya (TUAT), Yasunori Osana (Kumamoto Univ.), Takehumi Miyoshi (Wasalabo), Hironori Nakajo (TUAT) RECONF2023-30 |
In recent years, hardware acceleration for HPC and AI has become a challenge due to the lack of resources and the comple... [more] | RECONF2023-30 pp.46-51 |
| HWS | 2023-04-14 13:20 |
Oita | (Primary: On-site, Secondary: Online) |
Exploration of hardware Trojan detection through power supply current simulation Takafumi Oki, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) HWS2023-1 |
The recent development of information and communication technology has increased the demand for integrated circuit (IC) ... [more] | HWS2023-1 pp.1-5 |
| HWS, VLD | 2023-03-02 15:20 |
Okinawa | (Primary: On-site, Secondary: Online) |
Secure Cache System against On-Chip Threats Keisuke Kamahori, Shinya Takamaeda (UTokyo) VLD2022-95 HWS2022-66 |
In this paper, we propose a new threat model for secure processor design that considers on-chip threats. Also, we desi... [more] |
VLD2022-95 HWS2022-66 pp.113-118 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80 |
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] | VLD2022-57 RECONF2022-80 pp.7-12 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-28 13:05 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Development of ASIC Prototype Chip Evaluation System using FPGA-SoM Masashi Imai (Hirosaki Univ.), Kenji Kise (Tokyo Tech.), Tomohiro Yoneda (NII) VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42 |
An ASIC prototype chip requires the corresponding evaluation system based on its specification, resulting in lack of ver... [more] | VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42 pp.1-6 |
| HWS, ICD | 2022-10-25 11:50 |
Shiga | (Primary: On-site, Secondary: Online) |
Optical Microscopic Observation of Semiconductor Devices toward Hardware Trojan Detection Hirofumi Sakane, Junichi Sakamoto, Shinichi Kawamura (AIST), Makoto Nagata (Kobe Univ.), Yuichi Hayashi (NAIST) HWS2022-34 ICD2022-26 |
In this paper we focus on detection of hardware Trojan (HT) in semiconductor devices under a scenario with following ste... [more] | HWS2022-34 ICD2022-26 pp.23-28 |
| HWS, ICD | 2022-10-25 15:40 |
Shiga | (Primary: On-site, Secondary: Online) |
Hardware Acceleration of TFHE-based Adder by Controlling Error Yinfan Zhao, Ikeda Makoto (Univ. of Tokyo) HWS2022-40 ICD2022-32 |
Fully homomorphic encryption (FHE) is expected to be used in the secure delegating computation. The bootstrapping in the... [more] | HWS2022-40 ICD2022-32 pp.58-63 |
| IA, ICSS | 2022-06-24 10:25 |
Nagasaki | Univ. of Nagasaki (Primary: On-site, Secondary: Online) |
Application of Adversarial Examples to Physical ECG Signals Taiga Ono (Waseda Univ.), Takeshi Sugawara (UEC), Jun Sakuma (Tsukuba Univ./RIKEN), Tatsuya Mori (Waseda Univ./RIKEN/NICT) IA2022-11 ICSS2022-11 |
This work aims to assess the reality and feasibility of applying adversarial examples to attack cardiac diagnosis system... [more] | IA2022-11 ICSS2022-11 pp.61-66 |
| RECONF | 2022-06-07 14:50 |
Ibaraki | CCS, Univ. of Tsukuba (Primary: On-site, Secondary: Online) |
Vector Register Sharing Mechanism for Hardware Acceleration Tomoaki Tanaka, Ryousuke Higashi (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2022-5 |
In this paper, we present a vector register sharing mechanism that directly shares vector registers inside the processor... [more] | RECONF2022-5 pp.26-31 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:45 |
Online | Online | Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2021-52 CPSY2021-21 RECONF2021-60 |
This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the t... [more] | VLD2021-52 CPSY2021-21 RECONF2021-60 pp.19-24 |
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