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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CS, OCS (Joint) |
2020-01-17 13:50 |
Oita | Beppu Housensou Hotel (Oita Pref.) | Experimental evaluation of bandwidth allocation scheme on TDM-PON for co-existing HLS/LLS base stations Hiroko Nomura, Hirotaka Ujikawa, Hiroyuki Uzawa, Hirotaka Nakamura, Jun Terada (NTT)  CS2019-95 |
The ultra-high density deployment of small cells is being considered as a way of increasing the bandwidth of user equipm... [more] | CS2019-95 pp.39-44 |
| CS, CQ (Joint) |
2019-04-18 10:45 |
Osaka | Osaka Univ. Library | Bandwidth allocation of co-existing HLS/LLS base stations for TDM-PON system in 5G-MFH Hiroko Nomura, Hirotaka Ujikawa, Hiroyuki Uzawa, Hirotaka Nakamura, Jun Terada (NTT) CS2019-4 |
The ultra-high density deployment of small cells is being considered as a way of increasing the bandwidth of user equipm... [more] | CS2019-4 pp.19-24 |
| SIS | 2019-03-06 13:00 |
Tokyo | Tokyo Univ. Science, Katsushika Campus | Evaluation of an FPGA Implementation of MRCoHOG Feature using High-Level Synthesis Yuya Nagamine, Kazuki Yoshihiro, Hakaru Tamukoh (Kyutech) SIS2018-37 |
In this report, we evaluate a Field Programmable Gate Array (FPGA) implementation of Multiresolution Co-occurrence Histo... [more] | SIS2018-37 pp.1-4 |
| HWS, VLD | 2019-02-27 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan | Function-level Module Sharing with High-level Synthesis Ryohei Nozaki (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-100 HWS2018-63 |
High-Level Synthesis (HLS) which automatically synthesizes a Resister-Transfer Level (RTL) circuit from a behavioral des... [more] | VLD2018-100 HWS2018-63 pp.43-48 |
| HWS, VLD | 2019-02-27 14:55 |
Okinawa | Okinawa Ken Seinen Kaikan | High-Level Synthesis of the CHStone Benchmark Programs with SDSoC Takuya Adachi (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-101 HWS2018-64 |
In recent years, High-Level Synthesis (HLS), which automatically generates hardware circuits from software program, have... [more] | VLD2018-101 HWS2018-64 pp.49-54 |
| RECONF | 2018-05-24 15:20 |
Tokyo | GATE CITY OHSAKI | A design of autoscale mechanism using high level synthesis tool for autonomous distributed system Daichi Teruya, Hironori Nakajo (TUAT) RECONF2018-9 |
Since cloud computing has become widespread for various purposes, it is drawing attention to use FPGAs. When utilizing ... [more] |
RECONF2018-9 pp.45-50 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 09:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Overview of an HLS Framework Surpporting IoT/CPS Development Daichi Teruya, Hironori Nakajo (TUAT) VLD2017-77 CPSY2017-121 RECONF2017-65 |
We expect reduce CPU resource consumptions by offloading processing stream data, which are incessantly generated such a... [more] |
VLD2017-77 CPSY2017-121 RECONF2017-65 pp.89-94 |
| RECONF | 2017-09-26 11:00 |
Tokyo | DWANGO Co., Ltd. | [Invited Talk]
Increasing Productivity Using Xilinx Development Tools Louie Valena (Xilinx) RECONF2017-33 |
Xilinx offers several tools to ease the development of complex hardware-software systems. Tools such as Vivado HLS, SDSo... [more] | RECONF2017-33 pp.63-68 |
| RECONF | 2017-09-26 14:20 |
Tokyo | DWANGO Co., Ltd. | Implementing RISC-V with a Python-Based High-Level Synthesis Compiler Ryouzaburo Suzuki, Hiroaki Kataoka (Sinby) RECONF2017-36 |
During the last decade, the environment of field-programmable gate array (FPGA) development has changed rapidly, and the... [more] | RECONF2017-36 pp.81-86 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Hardware implementation of PLC Instructions by high level synthesis Ishigaki Yoshiki, Tanaka Tasuku, Fujieda Naoki, Ichikawa Shuichi (TUT) RECONF2016-43 |
The hardware implementation of instruction sequence is a method to conceal and to protect the intellectual property. ... [more] |
RECONF2016-43 pp.19-24 |
| RECONF | 2016-09-05 14:35 |
Toyama | Univ. of Toyama | The effect of the C ++ template meta-programming in high-level synthesis Kenichiro Mitsuda, Owada Hiroshi, Shinji Yamamoto (ISP) RECONF2016-27 |
In this talk, we introduce technique of high level synthesis using C++ template meta-programming. [more] | RECONF2016-27 pp.15-17 |
| RECONF | 2016-05-20 09:00 |
Kanagawa | FUJITSU LAB. | [Invited Talk]
Altera OpenCL SDK with Spectra-Q, the latest technology trend and the applications Spectra-Q: The latest technology and applications, including OpenCL SDK Yukitaka Takemura (Altera JP) RECONF2016-17 |
Recently the resources of FPGA have been increasing dramatically, and therefore a big improvement of the design tools co... [more] | RECONF2016-17 p.83 |
| RECONF | 2016-05-20 10:45 |
Kanagawa | FUJITSU LAB. | A Sound Field Visualizer with Java-based High Level Synthesis Tool and CoRAM Architecture Synthesis Framework Daichi Teruya, Daichi Miyazaki, Hironori Nakajo (TUAT) RECONF2016-20 |
Currently the number of devices which uses multiple sensors has been increasing due to recent significant interest on th... [more] | RECONF2016-20 pp.97-102 |
| VLD, IPSJ-SLDM | 2016-05-11 14:30 |
Fukuoka | Kitakyushu International Conference Center | A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4 |
In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] | VLD2016-4 pp.41-46 |
| VLD | 2016-02-29 16:15 |
Okinawa | Okinawa Seinen Kaikan | A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis Keisuke Inoue (KTC), Mineo Kaneko (JAIST) VLD2015-117 |
This paper discusses a high-level synthesis of new latch-based architecture, HLS-gls. The disadvantage of the conventio... [more] |
VLD2015-117 pp.37-42 |
| VLD | 2016-03-01 15:10 |
Okinawa | Okinawa Seinen Kaikan | FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] | VLD2015-127 pp.93-98 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 11:40 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Performance Comparison of FPGA Accelerators with Vivado HLS and PyCoRAM Yuma Kikutani (OPUCT), Thi Hong Tran, Shinya Takamaeda, Yasuhiko Nakashima (NAIST) CPSY2015-66 |
High-level synthesis (HLS) technology has been an attractive and efficient method for FPGA system development. In this ... [more] | CPSY2015-66 pp.27-32 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:35 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50 |
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] | VLD2015-54 DC2015-50 pp.99-104 |
| RECONF | 2015-09-18 14:30 |
Ehime | Ehime University | ZYNQ CLUSTER FOR CFD PARAMETRIC SURVEY Naru Sugimoto, Hideharu Amano (Keio Univ.) RECONF2015-39 |
FaSTAR (Fast Aerodynamics Routines) is a state of the art CFD (Computational Fluid Dynamics) software package to enable ... [more] | RECONF2015-39 pp.39-44 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 09:50 |
Kanagawa | Hiyoshi Campus, Keio University | A feasibility study on implementing numerical applications on FPGAs using Vivado HLS Hiroki Nakasone, Yasunori Osana, Yasunori Nagata (Univ of Ryukyu) VLD2014-135 CPSY2014-144 RECONF2014-68 |
FPGAs are one of hopeful candidate of accelerator for scientific computing in near future. There are many attempts in va... [more] | VLD2014-135 CPSY2014-144 RECONF2014-68 pp.145-150 |
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