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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 40 of 83 [Previous]  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SANE 2017-10-04
14:55
Tokyo Maison franco - japonaise (Tokyo) Interpretation of GPR survey of subsurface layer structure of the west coast fault zone at Aomori bay
Kazuki Fujisawa, Motoyuki Sato (Tohoku Univ.) SANE2017-46
In this report, we demonstrate that GPR(Ground Penetrating Radar)survey can analyze substance geological stratified stru... [more] SANE2017-46
pp.17-22
EMCJ 2016-09-16
11:55
Hyogo University of Hyogo TDR with Utility-Pole-Distance Resolution Considering Mode Conversion for Detection of Fault Type in Power Distribution Lines
Tohlu Matsushima, Takashi Hisakado, Osami Wada (Kyoto Univ.), Shinpei Oe, Tsuyoshi Sasaoka, Yasuharu Sakai (Kansai Electric Power Co. Inc.) EMCJ2016-52
It is necessary to detect a fault point in a distribution system for accident restoration in power grid. Applying a puls... [more] EMCJ2016-52
pp.13-18
VLD 2016-02-29
15:50
Okinawa Okinawa Seinen Kaikan ILP Based Synthesis of Soft-Error Tolerant Datapaths Considering Adjacency Constraint between Components
Junghoon Oh, Mineo Kaneko (JAIST) VLD2015-116
As the device size decreases, the reliability degradation due to soft-errors is becoming one of the serious issues in VL... [more] VLD2015-116
pp.31-36
DC 2016-02-17
10:50
Tokyo Kikai-Shinko-Kaikan Bldg. Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value
Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2015-88
As semiconductor technology is scaling down, open defects have often occurred at interconnect lines and vias. If logic v... [more] DC2015-88
pp.13-18
NC, NLP
(Joint)
2016-01-29
11:45
Fukuoka Kyushu Institute of Technology Fault tolerance of paralleled boost converters with WTA switching
Shouta Hakamada, Yasuo Murata, Toshimichi Saito (HU) NLP2015-140
This paper studies a paralleled system of boost converters with WTA-based switching rule.
The system exhibits multi-ph... [more]
NLP2015-140
pp.81-86
NS, RCS
(Joint)
2015-12-17
11:25
Ehime Matsuyama Community Center An Online Storage System Based on RAID
Takamasa Fujiwara, Jiahong Wang, Eiichiro Kodama, Toyoo Takata (Iwate Prefectural Univ.) NS2015-132
In recent years, with the wide spread of computers and smart phones (called terminals), it has become a general case tha... [more] NS2015-132
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-01
14:40
Nagasaki Nagasaki Kinro Fukushi Kaikan On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines
Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) VLD2015-42 DC2015-38
The effect of a resistive open results in small delay in an IC. It is difficult to test small delay since signal delay a... [more] VLD2015-42 DC2015-38
pp.31-36
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
10:10
Nagasaki Nagasaki Kinro Fukushi Kaikan An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components
Junghoon Oh, Mineo Kaneko (JAIST) VLD2015-62 DC2015-58
As the device size decreases, the reliability degradation due to soft-errors is becoming one of the serious issues in VL... [more] VLD2015-62 DC2015-58
pp.159-164
DC, CPSY 2015-04-17
09:50
Tokyo   A Proposal of Time-Lag-Less n-Fault-Tolerant Control System
Hitoshi Iwai CPSY2015-3 DC2015-3
In a conventional multi-modular majority voting redundancy for real-time hazard control the first processing step is tha... [more] CPSY2015-3 DC2015-3
pp.13-18
DC 2015-02-13
15:20
Tokyo Kikai-Shinko-Kaikan Bldg A Method of LFSR Seed Generation for Hierarchical BIST
Kosuke Sawaki, Satoshi Ohtake (Oita Univ.) DC2014-85
A linear feedback shift register (LFSR) is used as a test pattern generator of built-in self-test (BIST).
In BIST, alth... [more]
DC2014-85
pp.43-48
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
14:45
Oita B-ConPlaza Investigation of the area reduction of observation part and control part in TSV fault detection circuit
Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2014-72 DC2014-26
Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fa... [more] VLD2014-72 DC2014-26
pp.3-8
EMCJ 2014-07-10
15:45
Tokyo Kikai-Shinko-Kaikan Bldg. Feasibility of Fault-injected Timing Identification for Actual Cryptographic Devices Using Side-channel Information
Ko Nakamaura, Yu-ichi Hayashi, Takaaki Mizuki, Naofumi Homma, Takafumi Aoki, Hideaki Sone (Tohoku Univ.) EMCJ2014-23
The intentional electromagnetic interference (IEMI) fault-injection method using continuous sine waves causes random-byt... [more] EMCJ2014-23
pp.37-42
NS 2014-01-24
09:50
Okinawa Univ. of the Ryukyus A Secure Online Storage System Based on RAID
Takamasa Fuziwara, Jiahong Wang, Eiichiro Kodama, Toyoo Takata (Iwate Prefectural Univ.) NS2013-172
Recently, PC and mobile terminals are commonly available, multiple terminals per person become a very common case, and m... [more] NS2013-172
pp.53-58
KBSE 2013-05-31
14:45
Kanagawa Keio University Robustness Anlysis on Human-made Fault in Procedural Manuals
Naoyuki Nagatou (PRESYSTEMS), Takuo Watanabe (Tokyo Inst. of Tech.) KBSE2013-11
We adapt a formal approach for an investigation into robustness analysis on human-made faults in procedural manuals.Dete... [more] KBSE2013-11
pp.61-66
SS 2013-05-10
11:45
Kagawa Kagawa University (Saiwaimachi) An investigation of relationship between lines of comments and fault-proneness in small-sized programs
Hirohisa Aman (Ehime Univ.) SS2013-12
While comments are useful in enhancing the program readability, some comments would be used for
covering up complicated... [more]
SS2013-12
pp.67-72
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2013-03-14
15:05
Nagasaki   Self-Checking Carry Look-ahead Adder by Carry-bit Duplication
Akihiro Mitoma (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2012-98 DC2012-104
We propose a self-checking carry look-ahead adder, which can detect errors caused by a single stuck-at fault in the adde... [more] CPSY2012-98 DC2012-104
pp.277-282
DC 2013-02-13
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. Characteristic Analysis of Signal Delay for Resistive Open Fault Detection
Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84
When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistiv... [more] DC2012-84
pp.25-30
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-26
13:00
Fukuoka Centennial Hall Kyushu University School of Medicine [Invited Talk] High Field Reliability Using Built-In Self Test
Seiji Kajihara (Kyutech) VLD2012-65 DC2012-31
On-line test based on delay measurement at power-on/off time or at system idle time of a system allows us to detect dela... [more] VLD2012-65 DC2012-31
pp.37-42
MRIS, ITE-MMS 2012-07-20
09:50
Ibaraki Ibaraki Univ. Perfect Hcp Atomic-layer Stacking for Sputtered Co Film with c-plane Sheet Texture by Substrate Heating Sputtering
Naoki Nozawa, Shin Saito, Shintaro Hinata, Migaku Takahashi (Tohoku Univ.) MR2012-16
Effects of substrate heating of Co sputtered film with c-plane sheet texture on atomic-layer stacking were investigated ... [more] MR2012-16
pp.41-46
DC 2012-06-22
14:20
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg [Invited Talk] Empirical study for signal integrity-defects
Hiroshi Takahashi, Yoshinobu Higami (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. Tokushima) DC2012-12
We try to empirically study signal integrity-defects.
In this study, we analyze the resistive open fault that causes th... [more]
DC2012-12
pp.21-26
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