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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SIS, ITE-BCT | 2021-10-08 11:10 |
Online | Online | A Hardware-Oriented Algorithm for Person Recognition Processing using GMM-MRCoHOG features Ryogo Takemoto, Yuya Nagamine, Kazuki Yoshihiro (Kyutech), Masatoshi Shibata, Hideo Yamada (AISIN), Shuichi Enokida, Hakaru Tamukoh (Kyutech)  SIS2021-19 |
In this research, we focus on Gaussian Mixture Model-MultiResolution Co-occurrence Histograms of Oriented Gradients (GMM... [more] | SIS2021-19 pp.48-53 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 14:00 |
Kanagawa | Hiyoshi Campus, Keio Univ. | An FPGA NIC Based Distributed Ledger Caching for Blockchain Yuma Sakakibara, Kohei Nakamura (Keio Univ.), Hiroki Matsutani (Keio Univ./PRESTO/NII) VLD2016-99 CPSY2016-135 RECONF2016-80 |
(To be available after the conference date) [more] | VLD2016-99 CPSY2016-135 RECONF2016-80 pp.203-208 |
| CPSY, DC, IPSJ-ARC (Joint) [detail] |
2016-08-10 10:00 |
Nagano | Kissei-Bunka-Hall (Matsumoto) | A Low-Latency Offloading for Spark Streaming Using FPGA NIC Kohei Nakamura, Ami Hayashi, Hiroki Matsutani (Keio Univ.) CPSY2016-31 |
(To be available after the conference date) [more] | CPSY2016-31 pp.211-216 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-19 11:55 |
Kanagawa | Hiyoshi Campus, Keio University | A Low-Latency Batch Processing for Stream Data Using FPGA NIC Kohei Nakamura, Ami Hayashi, Hiroki Matsutani (Keio Univ.) VLD2015-80 CPSY2015-112 RECONF2015-62 |
(To be available after the conference date) [more] | VLD2015-80 CPSY2015-112 RECONF2015-62 pp.19-24 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 14:40 |
Kanagawa | Hiyoshi Campus, Keio University | FPGA-based Tsunami Simulator developed by using stream-computing hardware compiler Kohei Nagasu, Kentaro Sano (Tohoku Univ.), Fumiya Kono, Naohito Nakasato (The Univ. of Aizu) VLD2015-92 CPSY2015-124 RECONF2015-74 |
Method of Splitting Tsunami (MOST) is a numerical solver of Shallow Water Equations (SWEs), which is used for forecastin... [more] | VLD2015-92 CPSY2015-124 RECONF2015-74 pp.131-136 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 08:55 |
Kanagawa | Hiyoshi Campus, Keio University | Accelerating NOSQLs using FPGA NIC and In-Kernel Key-Value Cache Korechika Tamura, Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.) VLD2014-114 CPSY2014-123 RECONF2014-47 |
(To be available after the conference date) [more] | VLD2014-114 CPSY2014-123 RECONF2014-47 pp.7-12 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 15:15 |
Kanagawa | Hiyoshi Campus, Keio University | MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs Yuki Matsuda, Eri Ogawa, Tomohiro Misono (Tokyo Tech), Naoki Fujieda, Shuichi Ichikawa (TUT), Kenji Kise (Tokyo Tech) VLD2014-146 CPSY2014-155 RECONF2014-79 |
This paper describes the design and current development of MieruSys project which develops a future computer system with... [more] | VLD2014-146 CPSY2014-155 RECONF2014-79 pp.211-216 |
| CPSY, DC | 2012-04-10 13:50 |
Tokyo | The Automatic Code Optimization for High-Level Synthesis Mao Hatto, Takaaki Miyajima, Hideharu Amano (Keio Univ.) CPSY2012-3 DC2012-3 |
FPGA (Field Programmable Gate Array) has been applied to recent studies and products in high performance computation sys... [more] | CPSY2012-3 DC2012-3 pp.13-18 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:25 |
Miyazaki | NewWelCity Miyazaki | Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs Takayuki Akamine, Kenta Inakagata (Keio Univ.), Yasunori Osana (Ryukyu Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) RECONF2011-45 |
Computational Fluid Dynamics is an important tool to design aircraft components. FaSTAR is one of the most recent CFD pr... [more] | RECONF2011-45 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 13:25 |
Miyazaki | NewWelCity Miyazaki | A Scaling Method for a Large FU Array Accerlator on Multiple FPGAs Kodai Moritaka, Shunsuke Shitaoka, Kazuhiro Yoshimura, Jun Yao, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2011-44 |
We proposed previously Linear Array Pipeline Processor (LAPP), which can be used to map an inner loop of conventional V... [more] |
CPSY2011-44 pp.9-14 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 17:05 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Design of Dataflow Machine on Multiple FPGAs Kenta Inakagata, Hirokazu Morishita (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) VLD2010-115 CPSY2010-70 RECONF2010-84 |
Recently, computational science has been utilized in various eld such as physics, chemistry and economics. Since the co... [more] | VLD2010-115 CPSY2010-70 RECONF2010-84 pp.205-210 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-27 14:05 |
Kanagawa | Keio Univ (Hiyoshi Campus) | An Implementation of Fail-soft Systems with Adaptive Fault Tolerance using SRAM-based FPGAs Satoshi Fujie, Ryoji Noji, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2009-93 CPSY2009-75 RECONF2009-78 |
Fail-soft systems with reconfigurable devices, which recover themselves by repeating isolation of faulty portions with g... [more] | VLD2009-93 CPSY2009-75 RECONF2009-78 pp.149-154 |
| DC, CPSY | 2008-04-23 11:30 |
Tokyo | Tokyo Univ. | A Study on Reliability and Performance of FPGA-Based Fault Tolerant Systems Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) CPSY2008-4 DC2008-4 |
FPGAs (Field-Programmable Gate Arrays), which can implement arbitrary logic circuits any number of times by loading con... [more] |
CPSY2008-4 DC2008-4 pp.19-24 |
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