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Committee Date Time Place Paper Title / Authors Abstract Paper #
NC, IBISML, IPSJ-MPS, IPSJ-BIO [detail] 2019-06-17
16:45		 Okinawa Okinawa Institute of Science and Technology Embedded AI implementation
Tadaaki Shiraishi (MMS), Koji Kinoshita (Ehime Univ) NC2019-10		 In order to realize CNN on edge terminals and realize inference processing such as image recognition, it is important to... [more] NC2019-10
pp.35-40
IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2018-01-18
16:00		 Kanagawa Raiosha, Hiyoshi Campus, Keio University Integrated Machine Code Monitor on FPGA
Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.) VLD2017-73 CPSY2017-117 RECONF2017-61		 Machine code monitor is necessary for initial program development stage when implementing a new processor with unique IS... [more] VLD2017-73 CPSY2017-117 RECONF2017-61
pp.65-70
EST 2016-05-20
15:25		 Tokyo Kikai-Shinko-Kaikan Bldg. OpenCL-Based FPGA Platform for FDTD Computation
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuo Ohtera (Tohoku Univ.) EST2016-4		 We propose a FPGA accelerator for FDTD (finite difference time domain) computation based on a pipelined architecture to ... [more] EST2016-4
pp.17-20
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2012-11-28
13:00		 Fukuoka Centennial Hall Kyushu University School of Medicine A Case Study of Short-term Development of Cooperation with FPGA-based System by Introducing Distributed-object ORB Engine
Takeshi Ohkawa, Soshi Takano, Daichi Uetake, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba (Utsunomiya Univ.) RECONF2012-56		 We are developing “ORB Engine” which is a distributed-object middleware suitable for an FPGA, in order to reduce the ter... [more] RECONF2012-56
pp.51-56
 Results 1 - 4 of 4  /   
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