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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2014-04-17 10:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
66.3KIOPS-Random-Read 690MB/s-Sequential-Read Universal Flash Storage Device Controller with Unified Memory Extension Kenichiro Yoshii, Konosuke Watanabe, Nobuhiro Kondo, Kenichi Maeda, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki (Toshiba)  ICD2014-2 |
The world’s first embedded NAND storage device controller with Unified Memory (UM) has been demonstrated. UM achieves 2 ... [more] | ICD2014-2 pp.3-8 |
| SS, MSS | 2014-01-30 14:25 |
Aichi | An Efficient Parametric Execution Time Analysis of Real-Time Programs Using Approximation and its Evaluation Keisuke Sugihara, Akio Nakata (Hiroshima City Univ.) MSS2013-54 SS2013-51 |
For reusing real-time software in some different execution platform, it is useful to adjust the execution time of the pr... [more] | MSS2013-54 SS2013-51 pp.17-22 |
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| SDM, ICD | 2013-08-02 10:25 |
Ishikawa | Kanazawa University | 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Kazutaka Mori, Kazumasa Yanagisawa (Renesas Electronics) SDM2013-77 ICD2013-59 |
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achievi... [more] | SDM2013-77 ICD2013-59 pp.59-64 |
| SDM | 2012-03-05 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Basic Performance of a Logic-IP Compatible eDRAM with Cylinder Capacitors in Low-k/Cu BEOL Layers Ippei Kume, Naoya Inoue, Ken'ichiro Hijioka, Jun Kawahara, Koichi Takeda, Naoya Furutake, Hiroki Shirai, Kenya Kazama, Shin'ichi Kuwabara, Msasatoshi Watarai, Takashi Sakoh, Toshifumi Takahashi, Takashi Ogura, Toshiji Taiji, Yoshiko Kasama (Renesas Electronics) SDM2011-177 |
We have confirmed the basic performance of a Logic-IP compatible (LIC) eDRAM with cylinder capacitors in the low-k/Cu BE... [more] | SDM2011-177 pp.7-11 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2012-03-02 15:45 |
Miyagi | Design and implementation of distributed TLB mechanism for heterogeneous multi-core processors Daiki Kawase, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) CPSY2011-84 DC2011-88 |
Heterogeneous multi-core architecture, in which processor cores, memory modules, and I/O modules with various sizes, fu... [more] |
CPSY2011-84 DC2011-88 pp.85-90 |
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| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2012-03-02 16:15 |
Miyagi | Design and implementation of I/O control mechanism for heterogeneous multi-core processors Yuki Kawaguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) CPSY2011-85 DC2011-89 |
Heterogeneous multi-core architecture that consists of processors, memory modules, and I/O devices with various sizes, f... [more] | CPSY2011-85 DC2011-89 pp.91-96 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:55 |
Miyazaki | NewWelCity Miyazaki | Inhibiting Fluctuation of Execution Time of Real Time Tasks using Tightly Coupled Memory Tomoaki Ukezono, Yuanzhe LIU, Kiyofumi Tanaka (JAIST) CPSY2011-53 |
In real-time systems, predicting execution time of each task precisely takes the systems to significance of maintainin... [more] |
CPSY2011-53 pp.59-64 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 15:05 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption Junshi Takata (Kyushu Univ.), Tohru Ishihara (Kyoto Univ.), Koji Inoue (Kyushu Univ.) SIP2011-76 ICD2011-79 IE2011-75 |
The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given ... [more] | SIP2011-76 ICD2011-79 IE2011-75 pp.89-94 |
| ICD | 2011-04-18 10:50 |
Hyogo | Kobe University Takigawa Memorial Hall | [Invited Talk]
A Technical Trend and Embedded DRAM Technology for High-Performance NAND Flash Memories Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii (Toshiba) ICD2011-2 |
In this paper, first, the technical trend for high-bandwidth NAND flash memories is introduced. Second, an embedded DRAM... [more] | ICD2011-2 pp.7-12 |
| VLD | 2011-03-02 14:00 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-118 |
In hierarchical cache configurations, L1 cache uses LRU as cache replacement policy but L2 and/or L3 caches use FIFO du... [more] |
VLD2010-118 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 09:30 |
Fukuoka | Kyushu University | Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-64 DC2010-31 |
The number of sets, block size and associativity determine processor's cache configuration. Particularly in embedded sys... [more] | VLD2010-64 DC2010-31 pp.55-60 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 13:55 |
Fukuoka | Kyushu University | On a Prefetching Heterogeneous MDD Machine Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT) RECONF2010-41 |
This paper shows a heterogeneous multi-valued decision diagram machine~(HMDDM). First, we introduce a standard heteroge... [more] |
RECONF2010-41 pp.13-18 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-27 13:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | A Packet Classifier Using a Parallel Branching Program Machine Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Tech Corp.) VLD2009-92 CPSY2009-74 RECONF2009-77 |
A branching program machine~(BM) is a special-purpose processor that uses only two kinds of instructions: Branch and ... [more] |
VLD2009-92 CPSY2009-74 RECONF2009-77 pp.143-148 |
| MSS, CAS | 2009-11-27 13:00 |
Aichi | Nagoya University | Design and Evaluation of Graphics Accelerator System for Mobile Appliances Yasushi Nagai, Toru Owada (Hitachi), Tetsuo Takagi (Hitachi AD), Isao Takita (Hitachi) CAS2009-54 CST2009-27 |
Downsized and low power consumption graphics accelerator(GA) is necessary for the mobile appliance that have graphical u... [more] | CAS2009-54 CST2009-27 pp.53-57 |
| DC | 2009-06-19 10:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Note on Yield and Area Trade-offs for MBIST in SoC Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Michinobu Nakao, Iwao Suzuki (Renesas Tech Corp.) DC2009-11 |
In this study we evaluate the effectiveness of hardware overhead reduction of memory BIST and spare assignment algorithm... [more] | DC2009-11 pp.7-12 |
| VLD | 2009-03-12 13:00 |
Okinawa | Emulation of Sequential Circuits by a Parallel Branching Program Machine Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.) VLD2008-145 |
The parallel branching program machine~(PBM128) consists of 128 branching program machines~(BMs) and a programmable in... [more] |
VLD2008-145 pp.111-116 |
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| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2009-03-05 15:45 |
Niigata | Sado Island Integrated Development Center | Single-Cycle-Accessible Two-Level Cache Architecture Seiichiro Yamaguchi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-91 DC2008-82 |
A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the ener... [more] | CPSY2008-91 DC2008-82 pp.19-24 |
| SIS | 2009-03-05 15:45 |
Tokyo | [Special Talk]
System Realizations by Using Embedded Memories in FPGAs Yukihiro Iguchi (Meiji Univ.) |
FPGAs (Field Programmable Gate Arrays) have many embedded RAMs. We can use them for register files, FIFO (First In, Fi... [more] |
SIS2008-80 pp.49-54 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 12:20 |
Kanagawa | A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) VLD2008-115 CPSY2008-77 RECONF2008-79 |
In this paper, we propose an on-chip bus optimization algorithm for a multi-layer bus architecture. Our algorithm effici... [more] | VLD2008-115 CPSY2008-77 RECONF2008-79 pp.141-146 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:30 |
Fukuoka | Kitakyushu Science and Research Park | A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-76 DC2008-44 |
In an embedded system where a single application or a class of applications are repeatedly executed on a processor, its ... [more] | VLD2008-76 DC2008-44 pp.97-102 |
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