IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 16 of 16  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
16:35
Ehime Ehime Prefecture Gender Equality Center Non-stop embedded OS with Trace Buffer
Haruki Shishido, Yamasaki Nobuyuki (Keio Univ.) CPSY2019-51
Embedded system that is designed to operate a particular device has a feature that, in addition to power saving and reso... [more] CPSY2019-51
pp.77-82
SDM, ICD 2015-08-24
13:35
Kumamoto Kumamoto City [Invited Talk] Atom-Switch-Based Programmable Logic Array and ROM
Yukihide Tsuji, X Bai, Makoto Miyamura, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi (NEC), Nobuyuki Sugii (Hitachi), Hiromitsu Hada (NEC) SDM2015-61 ICD2015-30
We have proposed Nonvolatile Programmable Logic (NPL) and ROM using atom switch. Atom switch has unique properties, such... [more] SDM2015-61 ICD2015-30
pp.19-24
ICD, SDM 2014-08-04
13:55
Hokkaido Hokkaido Univ., Multimedia Education Bldg. [Invited Talk] STT-MRAM Development for Embedded Cache Memory
Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP) SDM2014-68 ICD2014-37
We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration ... [more] SDM2014-68 ICD2014-37
pp.35-38
SDM, ICD 2013-08-02
10:25
Ishikawa Kanazawa University 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique
Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Kazutaka Mori, Kazumasa Yanagisawa (Renesas Electronics) SDM2013-77 ICD2013-59
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achievi... [more] SDM2013-77 ICD2013-59
pp.59-64
ICD 2012-12-17
13:30
Tokyo Tokyo Tech Front [Invited Talk] High-performance STT-MRAM and Its Integration for Embedded Application
Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LESP) ICD2012-90
High-performance spin transfer torque MRAM (STT-MRAM) for embedded cache memories was developed, utilizing a top-pinned ... [more] ICD2012-90
pp.17-20
ICD 2012-04-24
11:15
Iwate Seion-so, Tsunagi Hot Spring (Iwate) [Invited Talk] Write-/Read- Disturb Issues and Circuit Solutions
Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki (Renesas Electronics) ICD2012-11
This paper describes some circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage agai... [more] ICD2012-11
pp.55-60
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-30
10:55
Miyazaki NewWelCity Miyazaki Inhibiting Fluctuation of Execution Time of Real Time Tasks using Tightly Coupled Memory
Tomoaki Ukezono, Yuanzhe LIU, Kiyofumi Tanaka (JAIST) CPSY2011-53
In real-time systems, predicting execution time of each task precisely
takes the systems to significance of maintainin... [more]
CPSY2011-53
pp.59-64
SDM, ICD 2011-08-26
15:05
Toyama Toyama kenminkaikan A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue
Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics) SDM2011-92 ICD2011-60
We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bi... [more] SDM2011-92 ICD2011-60
pp.109-114
DC 2009-06-19
10:45
Tokyo Kikai-Shinko-Kaikan Bldg. Note on Yield and Area Trade-offs for MBIST in SoC
Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Michinobu Nakao, Iwao Suzuki (Renesas Tech Corp.) DC2009-11
In this study we evaluate the effectiveness of hardware overhead reduction of memory BIST and spare assignment algorithm... [more] DC2009-11
pp.7-12
ICD 2008-04-18
13:55
Tokyo   A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme
Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-12
We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) a... [more] ICD2008-12
pp.63-68
ICD 2008-04-18
14:20
Tokyo   A 250-MHz 1-Mbit Embedded MRAM Macro Using 2T1MTJ Cell with Bitline Separation and Half-pitch Shift Architecture
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-13
A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-um standard CMOS process with 1.5V supply. Its clock frequency is ... [more] ICD2008-13
pp.69-74
ICD, ITE-IST 2007-07-26
17:05
Hyogo   Low power consumption of H.264/AVC decoder with dynamic voltage and frequency scaling
Yoshinori Sakata, Kentaro Kawakami, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2007-52
We propose an elastic pipeline architecture that can apply dynamic voltage scaling (DVS) to a dedicated hardware, and ap... [more] ICD2007-52
pp.89-94
ICD 2007-04-12
09:00
Oita   MRAM Cell Technology for High-speed SoCs
Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Kenichi Shimura, Naoki Kasai (NEC) ICD2007-1
We has succeeded in developing new MRAM cell technology suitable for high-speed memory macro embedded in next generation... [more] ICD2007-1
pp.1-5
ICD 2007-04-13
09:40
Oita   [Invited Talk] A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair s... [more] ICD2007-11
pp.59-64
ICD 2006-04-13
16:40
Oita Oita University [Panel Discussion] What is your urgent task in R/D of new embedded memories?
Hideto Hidaka (Renesas), Masao Taguchi (SPANSION), Takayuki Kawahara (Hitachi), Daisaburo Takashima (Toshiba), Shuichi Ueno (Renesas), Masashi Takata (Kanazawa Univ.), Masafumi Takahashi (Toshiba)
Recent advent of emerging memory devices circa 2000 has seen discussions directed mainly to stand-alone memory applicati... [more] ICD2006-9
p.49
ICD 2005-04-14
13:00
Fukuoka   [Invited Talk] *
Hiroyuki Yamauchi (Matsushita)
Based on the actual examples of where, how and why each memory is used, the representative embedded memories are classif... [more] ICD2005-6
pp.29-34
 Results 1 - 16 of 16  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan