| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SS | 2019-03-04 10:40 |
Okinawa | An improved LLF scheduling for reducing heap memory consumption in multiprocessor real-time system by considering laxity time Yuki Machigashira, Akio Nakata (Hirosima City Univ.)  SS2018-55 |
Real-time embedded systems are often designed as multitasking systems in order to improve responsiveness to multiple ext... [more] | SS2018-55 pp.19-24 |
|
| ICD | 2017-04-20 14:55 |
Tokyo | [Invited Lecture]
First demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and beyond Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi (Renesas Electronics), Digh Hisamoto (Hitachi) ICD2017-7 |
FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the ... [more] | ICD2017-7 pp.35-38 |
|
| SDM | 2017-01-30 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
First Demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and Beyond Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi (Renesas Electronics), Digh Hisamoto (Hitachi) SDM2016-134 |
FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the ... [more] | SDM2016-134 pp.17-20 |
| RECONF | 2016-05-19 17:30 |
Kanagawa | FUJITSU LAB. | [Invited Talk]
Overviews on key technologies to substantialize 'IoT society' Toshihiro Matsui, Hisashi Sekine, Hideki Hayashi, Hiroaki Ohkubo, Hirotaka Sunaguchi, Naoyuki Matsuo, Yoshitatsu Sato (NEDO TSC) RECONF2016-16 |
Regarding non-volatile memories, sensors, embedded software, and cyber security as the key components in the coming IoT ... [more] | RECONF2016-16 pp.77-82 |
| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ) ICD2014-82 CPSY2014-94 |
Demands for low energy microcontrollers which are used in sensor nodes have been increasing in recent years. Also most m... [more] | ICD2014-82 CPSY2014-94 p.43 |
| ICD, SDM | 2014-08-04 13:55 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
STT-MRAM Development for Embedded Cache Memory Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LEAP) SDM2014-68 ICD2014-37 |
We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration ... [more] | SDM2014-68 ICD2014-37 pp.35-38 |
| SDM, ICD | 2013-08-02 10:25 |
Ishikawa | Kanazawa University | 28nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Kazutaka Mori, Kazumasa Yanagisawa (Renesas Electronics) SDM2013-77 ICD2013-59 |
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achievi... [more] | SDM2013-77 ICD2013-59 pp.59-64 |
| ICD | 2012-12-17 13:30 |
Tokyo | Tokyo Tech Front | [Invited Talk]
High-performance STT-MRAM and Its Integration for Embedded Application Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Koji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida (LESP) ICD2012-90 |
High-performance spin transfer torque MRAM (STT-MRAM) for embedded cache memories was developed, utilizing a top-pinned ... [more] | ICD2012-90 pp.17-20 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:55 |
Miyazaki | NewWelCity Miyazaki | Inhibiting Fluctuation of Execution Time of Real Time Tasks using Tightly Coupled Memory Tomoaki Ukezono, Yuanzhe LIU, Kiyofumi Tanaka (JAIST) CPSY2011-53 |
In real-time systems, predicting execution time of each task precisely takes the systems to significance of maintainin... [more] |
CPSY2011-53 pp.59-64 |
| ICD | 2011-04-18 10:50 |
Hyogo | Kobe University Takigawa Memorial Hall | [Invited Talk]
A Technical Trend and Embedded DRAM Technology for High-Performance NAND Flash Memories Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii (Toshiba) ICD2011-2 |
In this paper, first, the technical trend for high-bandwidth NAND flash memories is introduced. Second, an embedded DRAM... [more] | ICD2011-2 pp.7-12 |
| SIS | 2009-03-05 15:45 |
Tokyo | [Special Talk]
System Realizations by Using Embedded Memories in FPGAs Yukihiro Iguchi (Meiji Univ.) |
FPGAs (Field Programmable Gate Arrays) have many embedded RAMs. We can use them for register files, FIFO (First In, Fi... [more] |
SIS2008-80 pp.49-54 |
|
| SIS | 2008-06-13 13:15 |
Hokkaido | An Architecture of Photo Core Transform in HD Photo Coding System for Embedded System of Various Bandwidths Koichi Hattori (Kyoto Univ.), Hiroshi Tsutsui (Osaka Univ.), Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) SIS2008-21 |
In this paper, we propose a novel architecture of photo core transform (PCT) which is used as transformation of image da... [more] | SIS2008-21 pp.39-44 |
|
| ICD | 2008-04-18 13:55 |
Tokyo | A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-12 |
We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) a... [more] | ICD2008-12 pp.63-68 |
|
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-27 17:45 |
Kagoshima | Allocation of Scratch-Pad Memory in Non-Preemptive Multi-Task Systems Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) DC2007-102 CPSY2007-98 |
In this paper, we propose three approaches to allocation of scratch-pad memory for non-preemptive fixed-priority multi-t... [more] | DC2007-102 CPSY2007-98 pp.109-114 |
|
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:30 |
Fukuoka | Kitakyushu International Conference Center | An ILP Model of Code Placement Problem for Minimizing the Energy Consumption in Embedded Processors Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) |
This paper formulates a code placement problem to optimize the total energy consumption of a CPU core, on-chip memories ... [more] | VLD2007-75 DC2007-30 pp.31-36 |
| ICD | 2007-04-12 09:00 |
Oita | MRAM Cell Technology for High-speed SoCs Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Kenichi Shimura, Naoki Kasai (NEC) ICD2007-1 |
We has succeeded in developing new MRAM cell technology suitable for high-speed memory macro embedded in next generation... [more] | ICD2007-1 pp.1-5 |
|
| ICD | 2006-04-13 16:40 |
Oita | Oita University | [Panel Discussion]
What is your urgent task in R/D of new embedded memories? Hideto Hidaka (Renesas), Masao Taguchi (SPANSION), Takayuki Kawahara (Hitachi), Daisaburo Takashima (Toshiba), Shuichi Ueno (Renesas), Masashi Takata (Kanazawa Univ.), Masafumi Takahashi (Toshiba) |
Recent advent of emerging memory devices circa 2000 has seen discussions directed mainly to stand-alone memory applicati... [more] | ICD2006-9 p.49 |
| ICD | 2005-04-14 13:00 |
Fukuoka | [Invited Talk]
* Hiroyuki Yamauchi (Matsushita) |
Based on the actual examples of where, how and why each memory is used, the representative embedded memories are classif... [more] | ICD2005-6 pp.29-34 |
|
[Return to Top Page]