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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 15:20 |
Ehime |
Ehime Prefecture Gender Equality Center |
A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs Yuta Ishiyama, Toshinori Hosokawa, Yuki Ikegaya (Nihon Univ.) VLD2019-43 DC2019-67 |
One of the challenges on VLSI testing is to reduce the area overhead and test application time of design-for-testability... [more] |
VLD2019-43 DC2019-67 pp.133-138 |
DC |
2019-02-27 14:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Compaction Method for Test Sensitization State in Controllers Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.) DC2018-80 |
One of the challenges on VLSI testing is to reduce the area overhead of design-for-testability and to increase the fault... [more] |
DC2018-80 pp.55-60 |
DC |
2013-06-21 13:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10 |
In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] |
DC2013-10 pp.1-6 |
RECONF |
2011-05-13 13:55 |
Hokkaido |
Hokkaido Univ. (Faculty of Eng., B3 Bldg.) |
A Homogeneous Routing Architecture for Efficient FPGA Design Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-19 |
In previous work, we have designed a prototype chip of island-style FPGA architecture. This architecture has very comple... [more] |
RECONF2011-19 pp.109-114 |
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