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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IN, NV (Joint) |
2015-07-16 14:50 |
Hokkaido | Hokkaido University | Dynamic Reconfiguration of P2P Streaming Networks using Network Motifs Kazuki Ono, Noriko Matsumoto, Norihiko Yoshida (Saitama Univ.)  IN2015-27 |
In recent years, Peer-to-Peer (P2P) streaming networks is becoming increasing popular as it not only fault tolerant, but... [more] | IN2015-27 pp.25-30 |
| ICSS | 2014-11-27 14:20 |
Miyagi | Tohoku Gakuin University (Tagajo Campus) | Dynamic Zoning of the Industrial Control System for Security improvement Wataru Machii, Isao Kato, Masahito Koike, Masafumi Matta, Tomomi Aoyama, Ichiro Koshijima, Yoshihiro Hashimoto (NIT) ICSS2014-52 |
In the previous paper, our authors proposed a design methodology of zones and conduits not only to isolate incidents cau... [more] | ICSS2014-52 pp.7-12 |
| ICD, SDM | 2014-08-04 10:50 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | A 28nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori (Renesas Electronics) SDM2014-64 ICD2014-33 |
This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application pro... [more] | SDM2014-64 ICD2014-33 pp.11-16 |
| NS, IN (Joint) |
2014-03-07 10:20 |
Miyazaki | Miyazaki Seagia | Blocking off Reflective DoS Attacks by Dynamic Packet Filter Yuichi Sudo, Kunio Hato (NTT) IN2013-181 |
Recently, danger of reflective DoS attacks is growing. For example, attacking traffic more than 300 Gbps of reflective D... [more] | IN2013-181 pp.223-228 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 10:25 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array Toru Katagiri, Hideharu Amano (Keio Univ.) VLD2013-122 CPSY2013-93 RECONF2013-76 |
Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high... [more] | VLD2013-122 CPSY2013-93 RECONF2013-76 pp.119-124 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 11:05 |
Kagoshima | [Invited Talk]
Toward VLSI Reliability Enhancement by Reconfigurable Architecture Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.) VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51 |
Owing to wide spread of VLSI systems, a failure of the VLSIs may lead critical issue in our daily life. Especially in so... [more] | VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51 p.183(VLD), p.81(CPM), p.81(ICD), p.27(CPSY), p.183(DC), p.69(RECONF) |
|
| MSS, CAS, IPSJ-AL [detail] | 2013-11-06 14:00 |
Iwate | Development of specification language for dynamic embedded systems Satoshi Yamane, Makoto Sakai (Kanazawa Univ.) CAS2013-58 MSS2013-37 |
Embedded systems input signals from external environments, and tasks communicate with other tasks, also tasks behave c... [more] |
CAS2013-58 MSS2013-37 pp.23-28 |
|
| RCS | 2013-10-17 11:00 |
Tokyo | Sophia Univ. | A Study on Downlinik/Uplink Power Control Technique for Dynamic TDD based Small Cell Systems Hiroki Takahashi, Kazunari Yokomakura, Kimihiko Imamura (Sharp) RCS2013-146 |
This paper proposes a downlink (DL)/uplink (UL) transmission power control (TPC) scheme for dynamic time division duplex... [more] | RCS2013-146 pp.25-30 |
| RECONF | 2013-09-19 14:50 |
Ishikawa | Japan Advanced Institute of Science and Technology | Considerations of Constantize for Entries in Associative Memories Using Dynamic Partial Reconfiguration Tomoaki Ukezono, Koichi Araki (JAIST) RECONF2013-36 |
In general, memories which can be referenced by associative search will enlarge hardware size and extend delay for refer... [more] | RECONF2013-36 pp.97-102 |
| RECONF | 2013-05-20 17:40 |
Kochi | Kochi Prefectural Culture Hall | Flexible reliability mixed-grained reconfigurable architecture supporting behavioral synthesis Hiroaki Konoura, Dawood Alnajjar (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Imagawa (Kyoto Univ.), Shinichi Noda, Kazutoshi Wakabayashi (NEC), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2013-8 |
This paper proposes a mixed-grained reconfigurable architecture that supports C-based behavioral synthesis and flexibl... [more] |
RECONF2013-8 pp.41-46 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 13:25 |
Kanagawa | A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) VLD2012-130 CPSY2012-79 RECONF2012-84 |
Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow ... [more] | VLD2012-130 CPSY2012-79 RECONF2012-84 pp.135-140 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 17:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | [Keynote Address]
Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics) VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 |
DRP features two dimensional array of tiny processors and memories, onto which applications are compiled and mapped as a... [more] | VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 p.163(VLD), p.29(CPM), p.29(ICD), p.45(CPSY), p.163(DC), p.15(RECONF) |
| RECONF | 2012-09-18 16:30 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | Study of "fine-grain dynamic partial reconfiguration mechanism" on FPGA Kunihiro Ueda, Naoki Kawamoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2012-34 |
Dynamic and partial reconfiguration (DRP) on SRAM-based FPGAs has received increasing attention, since Xilinx Inc. start... [more] | RECONF2012-34 pp.61-66 |
| RECONF | 2012-09-19 09:00 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | Effects of Power Saving by Dynamic Partial Reconfiguration in Video Shape Detection Processing Naoki Kawamoto, Kunihiro Ueda, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2012-36 |
Some of recent FPGAs have the functionality of dynamic partial reconfiguration. By using this functionality, it is expec... [more] | RECONF2012-36 pp.73-78 |
| DC, CPSY (Joint) |
2012-08-03 09:30 |
Tottori | Torigin Bunka Kaikan | A development scheduling simulater for reconfiguable system Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2012-19 |
Reconfigurable Computing Systems (RC Systems) are used to high-speed applications processing. We have investigating the ... [more] | CPSY2012-19 pp.61-66 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:45 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:30 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-73 ICD2011-76 IE2011-72 |
Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-... [more] | SIP2011-73 ICD2011-76 IE2011-72 pp.73-76 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:55 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-74 ICD2011-77 IE2011-73 |
Accelerator cores in low-power heterogeneous multicore processors have multiple memory modules to increase the data acce... [more] | SIP2011-74 ICD2011-77 IE2011-73 pp.77-82 |
| RECONF | 2011-09-26 15:30 |
Aichi | Nagoya Univ. | Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers Krzysztof Jozwik, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-29 |
Preemption techniques for HW (hardware) tasks have been studied in order to improve their responsiveness and to allow ... [more] |
RECONF2011-29 pp.43-48 |
| RECONF | 2011-09-27 09:50 |
Aichi | Nagoya Univ. | A Basic Implementation of LUT-based Dynamic and Partial Reconfiguration from Remote Site Hiroyuki Kawai (Hamamatsu Photonics), Moritoshi Yasunaga (Tsukuba Univ.) RECONF2011-34 |
In this study we implement a mechanism that makes it possible to execute dynamic and partial reconfigurationfrom remote ... [more] | RECONF2011-34 pp.69-74 |
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