| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, OME | 2023-04-22 15:35 |
Okinawa | Okinawaken Seinen Kaikan (Primary: On-site, Secondary: Online) |
[Invited Talk]
Double gate thin-film transistors on glass substrates Akito Hara, Kaisei Nomura, Akihisa Nagayoshi, Masahide Nitta, Syo Suzuki, Yuto Ito (Tohoku Gakuin Univ.)  SDM2023-16 OME2023-16 |
The aim of our research is to realize high performance and functional thin-film transistors (TFTs) on glass substrates. ... [more] | SDM2023-16 OME2023-16 pp.59-62 |
| SDM, OME | 2016-04-09 11:15 |
Okinawa | Okinawa Prefectural Museum & Art Museum | Self-Aligned Four-Terminal Metal Double-Gate LT Ni-SPC Poly-Si TFT with High-k Gate Stack Syota Nibe, Hiroki Ohsawa, Akito Hara (Tohoku Gakuin Univ.) SDM2016-15 OME2016-15 |
Self-aligned four-terminal (4T) metal double-gate (MeDG) low-temperature (LT) polycrystalline-silicon (poly-Si) thin fil... [more] | SDM2016-15 OME2016-15 pp.61-65 |
| SDM | 2013-11-15 11:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Theoretical Modeling of Double-Gate Lateral Tunnel FET Yasuhisa Omura, Daiki Sato, Shingo Sato (Kansai Univ.), Abhijit Mallik (Univ. of Calcuitta) SDM2013-109 |
This paper proposes a physics-based analytical device model with the non-local effect for the double-gate lateral TFET i... [more] | SDM2013-109 pp.55-60 |
| ICD, ITE-IST | 2013-07-05 16:50 |
Hokkaido | San Refre Hakodate | A Study on 1/f Noise Characteristic in Independent-Double-Gate-FinFET Hideo Sakai (Keio Univ.), Shin-ichi O'uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Yuki Ishikawa, Junichi Tsukada, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Meishoku Masahara (AIST), Hiroki Ishikuro (Keio Univ.) ICD2013-43 |
In this work, we measured 1/f noise of Independent-Double-Gate- (IDG-) FinFET which has two independent gates. Flicker n... [more] | ICD2013-43 pp.119-124 |
| SDM, OME | 2012-04-27 16:50 |
Okinawa | Okinawa-Ken-Seinen-Kaikan Bldg. | Self-Aligned Planar Metal Double-Gate Polycrystalline-Silicon Thin-Film Transistors Fabricated at Low Temperature on Glass Substrate Hiroyuki Ogata, Kenji Ichijo, Kenji Kondo, Yasunori Okabe, Yusuke Shika, Shinya Kamo, Akito Hara (Tohoku Gakuin Univ.) SDM2012-9 OME2012-9 |
A multigate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) is one of the recent topics in the field of Si ... [more] | SDM2012-9 OME2012-9 pp.41-44 |
| ICD | 2009-12-14 13:30 |
Shizuoka | Shizuoka University (Hamamatsu) | [Poster Presentation]
Reducing pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2009-78 |
We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] | ICD2009-78 pp.13-18 |
| VLD | 2009-03-13 15:15 |
Okinawa | Reduced pattern area technology of 3D transistor for system LSI Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2008-167 |
We designed 1 bit Full Adder with FinFET, Double-Gate transistor. FinFET, Double-Gate transistor, Stacked type transisto... [more] | VLD2008-167 pp.243-248 |
|
| SDM [detail] | 2008-11-14 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A 3D simulator for designing next generation semiconductor devices, Part 1
-- Development of a strongly stable simulator -- Shogo Sakurai, Zhu Riming, Masahiro Sato, Ken Yamaguchi (AdvanceSoft Corp.) SDM2008-173 |
In listed requirements of device simulator for designing of semiconductor devices in next generation, we focus on one of... [more] | SDM2008-173 pp.27-32 |
| SDM, ED | 2008-07-10 09:15 |
Hokkaido | Kaderu２・７ | Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memories Doo-Hyun Kim, Il Han Park, Byung-Gook Park (Seoul National Univ.) ED2008-55 SDM2008-74 |
This paper presents a detailed study of the retention characteristics in scaled multi-bit SONOS flash memories. By calcu... [more] | ED2008-55 SDM2008-74 pp.81-84 |
| VLD, ICD | 2008-03-07 16:10 |
Okinawa | TiRuRu | New technology of independent-gate controlled Double-Gate transistor for system LSI Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-168 ICD2007-191 |
New design technology of independent-gate controlled Double-Gate transistor realized high density design more than FinFE... [more] | VLD2007-168 ICD2007-191 pp.69-74 |
| VLD, ICD | 2008-03-07 16:35 |
Okinawa | TiRuRu | New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-169 ICD2007-192 |
New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controll... [more] | VLD2007-169 ICD2007-192 pp.75-80 |
| ED, SDM | 2008-01-31 09:50 |
Hokkaido | Proposal of CdTe X-ray image sensor driven by FEA with focusing electrode Yuichiro Hanawa, Takuya Sakata, Takashi Soda, Gui Han, Hisashi Morii, Katsumi Matsubara, Susumu Yamashita (RIE. Shizuoka Univ.), Masayoshi Nagao, Seigo Kanemaru (AIST), Yoichiro Neo, Toru Aoki, Hidenori Mimura (RIE. Shizuoka Univ.) ED2007-246 SDM2007-257 |
We proposed a novel CdTe X-ray image sensor, which was driven by the FEA, to obtain high spatial resolution X-ray images... [more] | ED2007-246 SDM2007-257 pp.47-50 |
|
| OME | 2006-07-27 14:20 |
Kanagawa | Low voltage operation of organic CMOS inverter circuit with double-gate structure Kazuki Hizu, Tsuyoshi Sekitani (Univ. Tokyo), Youko Shimada, Joe Otsuki (Nihon Univ.), Makoto Takamiya, Takayasu Sakurai, Takao Someya (Univ. Tokyo) |
We reported that threshold voltage of organic transistors can be controlled with double-gate structures. By applying tha... [more] | OME2006-56 pp.33-35 |
|
| ICD, VLD | 2006-03-10 16:00 |
Okinawa | Impact of Three-Dimensional Transistor on the pattern area reduction for ULSI Shigeyoshi Watanabe (Shonan Inst. of Tech.) |
The impact of three-dimensional transistors, double-gate transistor, FinFET, and surrounding gate transistor (SGT) on th... [more] | VLD2005-133 ICD2005-250 pp.67-72 |
|
[Return to Top Page]