Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, HWS, ICD |
2024-02-28 16:45 |
Okinawa |
(Primary: On-site, Secondary: Online) |
Research on Routing Method for Spacer-Is-Metal Type Self-Aligned Double Patterning Koki Tanaka, Takuto Amari, Kunihiro Fujiyoshi (TUAT) VLD2023-105 HWS2023-65 ICD2023-94 |
SIM type Self-Aligned Double Patterning is one of the process technologies wiring with a pitch half of the exposure-poss... [more] |
VLD2023-105 HWS2023-65 ICD2023-94 pp.36-41 |
HWS, VLD |
2019-02-27 13:30 |
Okinawa |
Okinawa Ken Seinen Kaikan |
Routing Algorithm to Achieve Circular Wire for SIM-Type SADP Shun Akatsuka, Kunihiro Fujiyoshi (TUAT) VLD2018-98 HWS2018-61 |
Wires of Spacer-Is-Metal (SIM) type Self-Aligned Double Patterning (SADP) is peculiar since wires is circular when dummy... [more] |
VLD2018-98 HWS2018-61 pp.31-36 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 14:40 |
Hiroshima |
Satellite Campus Hiroshima |
Improved Routing Method for Two Layer Self-Aligned Double Patterning Shoya Tamura, Kunihiro Fujiyoshi (TUAT) VLD2018-45 DC2018-31 |
Self-Aligned Double Patterning (SADP) enables us to fabricate fine wiring under ArF immersion lithography. However, when... [more] |
VLD2018-45 DC2018-31 pp.37-42 |
CAS, SIP, MSS, VLD |
2018-06-15 15:25 |
Hokkaido |
Hokkaido Univ. (Frontier Research in Applied Sciences Build.) |
Routing Algorithm to Achieve Circular Wire for SIM-Type SADP Shun Akatsuka, Kunihiro Fujiyoshi (TUAT) CAS2018-30 VLD2018-33 SIP2018-50 MSS2018-30 |
Wires of Spacer-Is-Metal (SIM) type Self-Aligned Double Patterning (SADP) is peculiar since wires is circular when dummy... [more] |
CAS2018-30 VLD2018-33 SIP2018-50 MSS2018-30 pp.155-160 |
VLD |
2017-03-02 11:20 |
Okinawa |
Okinawa Seinen Kaikan |
Efficient Local Pattern Modification Method using FM Algorithm in LELE Double Patterning Atsushi Ogashira, Shimpei Sato, Atsushi Takahashi (Tokyo TECH) VLD2016-113 |
In current semiconductor design, high quality and short time design is required.
In an advanced lithography technology... [more] |
VLD2016-113 pp.67-72 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 11:20 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus |
SADP-Cut Aware Two-color Grid Routing Hatsuhiko Miura, Mitsuru Hasegawa, Kunihiro Fujiyoshi (TUAT) VLD2016-58 DC2016-52 |
Self-Aligned Double Patterning (SADP) is one of the promising manufacturing option to overcome the limit of miniaturizat... [more] |
VLD2016-58 DC2016-52 pp.85-90 |
VLD, IPSJ-SLDM |
2016-05-11 10:25 |
Fukuoka |
Kitakyushu International Conference Center |
Self-Aligned Double Patterning-Aware Two-color Grid Routing Hatsuhiko Miura, Mitsuru Hasegawa, Taku Hirukawa, Kunihiro Fujiyoshi (TUAT) VLD2016-2 |
Self-Aligned Double Patterning (SADP) is one of the promising manufacturing option to overcome the limit of miniaturizat... [more] |
VLD2016-2 pp.5-10 |
VLD |
2014-03-04 13:50 |
Okinawa |
Okinawa Seinen Kaikan |
Local Pattern Modification Method for Lithographical ECO in Double Patterning Yutaro Miyabe, Atsushi Takahashi, Tomomi Matsui (Tokyo Inst. of Tech.), Yukihide Kohira (Univ. of Aizu), Yoko Yokoyama (Toshiba) VLD2013-149 |
In advanced semiconductor manufacturing processes, even though a pattern is generated according to
a design rule, hot s... [more] |
VLD2013-149 pp.87-92 |
VLD |
2014-03-04 14:40 |
Okinawa |
Okinawa Seinen Kaikan |
Self-Aligned Double and Quadruple Patterning-Aware Grid Routing Chikaaki Kodama (Toshiba), Hirotaka Ichikawa (Toshiba Microelectronics), Fumiharu Nakajima, Koichi Nakayama, Shigeki Nojima, Toshiya Kotani (Toshiba) VLD2013-151 |
Self-Aligned Double and Quadruple Patterning (SADP, SAQP) are leading candidates for sub-$20~nm$ and sub-$14~nm$ node an... [more] |
VLD2013-151 pp.99-104 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 13:00 |
Miyazaki |
NewWelCity Miyazaki |
Layout Methodology for Self-Alinged Double Patterning Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto (Toshiba) VLD2011-76 DC2011-52 |
We propose a new layout method for the damascene process of
self-aligned double patterning (SADP).
In this method, w... [more] |
VLD2011-76 DC2011-52 pp.141-146 |