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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-17
14:30		 Kanagawa Keio Univ (Hiyoshi Campus) Design and check a ROHM 0.18μm chip with Alliance VHDL toolset -- Trial the layout and netlist check tools --
Tatsuya Hosokawa, Hiroshi Imai, Naohiko Shimizu (Tokai Univ.) VLD2010-93 CPSY2010-48 RECONF2010-62		 In this paper, We describe about LSI design with an Alliance CAD tools. An alliance CAD tools is not
enough description... [more]		 VLD2010-93 CPSY2010-48 RECONF2010-62
pp.55-61
IPSJ-DC, LOIS, IEE-IIS [detail] 2009-07-30
13:30		 Akita Akita Univ. Preparing and management of physical restriction model
Akihiro Goto, Masashi Nagae (Mitsubishi Electric Corp.), Hirokazu Taki (Wakayama Univ.) 		The authors now constructed physical restriction model, and the model which manages the restriction (designing process).... [more] LOIS2009-10
pp.7-10
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2008-11-18
13:00		 Fukuoka Kitakyushu Science and Research Park Improving the Accuracy of Rule-based Equivalence Checking of High-level Desciptions by Identifying Potential Internal Equivalences
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) 		Rule-based equivalence checking of high-level design descriptions proves the equivalence of two high-level design descri... [more] VLD2008-78 DC2008-46
pp.109-114
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