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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2011-02-14 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Pattern Generation for Highly Accurate Delay Testing Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST)  DC2010-64 |
We propose a new faster-than-at-speed test method to detect small delay defects. As semiconductor technology is scaling ... [more] | DC2010-64 pp.33-38 |
| AP, ITE-BCT | 2011-02-09 15:05 |
Tokyo | NHK Science Tech. Research Lab. | A Reverberation Chamber to Realize Multipath-rich Environment [III]
-- Environment Control by Electromagnetic Wave Absorbing Sheet: Part 2 -- Rizwan Arif, Masahiro Shinozawa, Ichiro Oshima, Yoshio Karasawa (Univ. of Electro-Comm.) AP2010-164 |
Creation of multipath-rich propagation environment is needed to evaluate the performance of a MIMO communication termina... [more] | AP2010-164 pp.19-23 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | [Invited Talk]
Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.) |
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more] | |
| DC | 2010-02-15 13:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reduction of execution times and areas for delay measurement by subtraction Toru Tanabe, Hirohisa Minato, Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.) DC2009-71 |
Since VLSI is in nanoscase size, high density and high speed in recent years, small-delay defects which change propagati... [more] | DC2009-71 pp.39-44 |
| DC | 2010-02-15 14:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Seed Selection for High Quality Delay Fault Test in BIST Akira Taketani, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-74 |
In this paper, we target a scan BIST architecture that consists of LFSR, phase shifter and MISR, and propose a method to... [more] | DC2009-74 pp.57-62 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 14:25 |
Kochi | Kochi City Culture-Plaza | A Path Selection Method of Delay Test for Transistor Aging Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST) VLD2009-65 DC2009-52 |
With the advanced VLSI process technology, it is important for reliability of VLSIs to deal with faults caused by aging.... [more] | VLD2009-65 DC2009-52 pp.167-172 |
| DC | 2009-02-16 15:45 |
Tokyo | Resource Binding to Minimize the Number of RTL Paths Yuichi Uemoto, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Scie and Tech.) DC2008-77 |
Though path delay testing is promising to detect small delay in a VLSI circuit, it has a practical problem that the numb... [more] | DC2008-77 pp.55-60 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:55 |
Fukuoka | Kitakyushu Science and Research Park | [Poster Presentation]
A Hybrid Delay Scan forDelay Testing Based on Propagation Dominance Tomomi Nuwa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2008-81 DC2008-49 |
The hybrid delay scan design [1], where part of FFs can be controlled as skewed-load ones, is an effective method for a... [more] |
VLD2008-81 DC2008-49 pp.127-132 |
| NS | 2008-10-24 10:45 |
Osaka | Kansai University | Data Forwarding System with Multiple Data Channels for Challenged Network Akira Nagata, Shinya Yamamura (NICT), Masato Uchida, Masato Tsuru (Kyushu Inst. of Tech.) NS2008-85 |
The present paper introduces the Proxy Data Transfer system, which enables file transfer applications to work over long ... [more] | NS2008-85 pp.99-104 |
| ICD, SDM | 2008-07-17 10:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A small-delay defect detection technique for dependable LSIs Koichiro Noguchi, Koichi Nose (NEC), Toshinobu Ono (NECEL), Masayuki Mizuno (NEC) SDM2008-132 ICD2008-42 |
As continuous process scaling produces large-scale chips, small-delay defects become one of the major chip-reliability l... [more] | SDM2008-132 ICD2008-42 pp.23-28 |
| DC, CPSY | 2008-04-23 16:15 |
Tokyo | Tokyo Univ. | Soft Error Hardened FF Capable of Detecting Wide Error Pulse Shuangyu Ruan, Kazuteru Namba, Hideo Ito (Chiba-Univ.) CPSY2008-9 DC2008-9 |
In the recent high-density and low-power VLSIs，occurrence of soft errors becomes significant problems．Recently，soft erro... [more] | CPSY2008-9 DC2008-9 pp.49-54 |
| DC | 2008-02-08 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | RTL False Path Identification Using High Level Synthesis Information Naotsugu Ikeda, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST) DC2007-77 |
This paper proposes a method of RTL false path identification using high level synthesis information. By using the false... [more] | DC2007-77 pp.63-68 |
| IA | 2007-07-20 14:00 |
Kyoto | room1 (J501) on 5th floor in J bldg, Kyoto Women's University | Inferring the Internet topology in Japan through end-to-end latency measurement Yutaka Kikuchi (Kochi Univ. of Tech.), Yoriko Fujii (Keio Univ.), Masateru Yamamoto, Kenichi Nagami, Ikuo Nakagawa (Intec Netcore) IA2007-27 |
In this paper, we try to infer the Japanese Internet topology based on collected delay data from four ISPs. We first pro... [more] | IA2007-27 pp.103-108 |
| CPSY, DC | 2007-04-20 13:45 |
Tokyo | Soft Error Hardend Latch Scheme for Enhanced Scan Based Delay Fault Testing Takashi Ikeda, Kazuteru Namba, Hideo Ito (Chiba Univ.) CPSY2007-1 DC2007-1 |
In recent high-density, high-speed and low-power VLSIs, soft errors and delay faults frequently occur. Therefore, soft e... [more] | CPSY2007-1 DC2007-1 pp.1-6 |
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| VLD, ICD, DC, IPSJ-SLDM | 2005-12-01 09:30 |
Fukuoka | Kitakyushu International Conference Center | Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure Kosuke Yabuki, Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a method of path delay fault testing for application-specific interconnects in field-programmable ga... [more] | VLD2005-61 ICD2005-156 DC2005-38 pp.1-6 |
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