Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
AP (2nd) |
2013-05-31 13:30 |
Ehime |
Matsuyama Multi-Purpose Community Center |
Measurement of the phase center of UWB antennas for calibration of ground penetrating radar systems Hai Liu (Tohoku Univ.), Jie Chen (CAS), Motoyuki Sato (Tohoku Univ.) |
The precise knowledge of the antenna phase center is of great importance for the signal processing and ranging using a r... [more] |
|
NS |
2013-05-17 10:25 |
Kanagawa |
The Graduate Univ. for Advanced Studies |
Congestion Control with Limited Queue Fluctuation in Data Center Networks Yuki Tanisawa, Takeshi Kimura, Hiroki Mihara, Miki Yamamoto (Kansai Univ.) NS2013-26 |
Data center network is composed of high-speed Ethernet extended in a limited area of a data center building, so its RTT ... [more] |
NS2013-26 pp.77-82 |
VLD, IPSJ-SLDM |
2013-05-16 16:00 |
Fukuoka |
Kitakyushu International Conference Center |
A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] |
VLD2013-9 pp.67-72 |
RCS, IN (Joint) |
2013-05-16 10:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Reservation-based Random Access Protocol with Contention Resolution by Multiuser Detection Tomoya Tandai, Hiroshi Suzuki, Kazuhiko Fukawa, Satoshi Suyama (Tokyo Inst. of Tech.) RCS2013-24 |
This report proposes a novel reservation-based random access protocol with contention resolution by multiuser detection ... [more] |
RCS2013-24 pp.7-12 |
DC |
2013-02-13 13:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Characteristic Analysis of Signal Delay for Resistive Open Fault Detection Hiroto Ohguri, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2012-84 |
When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance. However, a resistiv... [more] |
DC2012-84 pp.25-30 |
DC |
2013-02-13 13:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
On Fault detection method considering adjacent TSVs for a delay fault in TSV Masanori Nakamura, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ.of Tokushima) DC2012-85 |
We propose a fault detection method for a TSV (through-Silicon via) considering adjacent TSVs for detecting delay caused... [more] |
DC2012-85 pp.31-36 |
EMM |
2013-01-30 13:00 |
Miyagi |
Tohoku Univ. |
Detection of Tampering in Speech Signals with Digital-Audio Watermarking Technique based on Cochlear delay Masashi Unoki, Shengbei Wang, Ryota Miyauchi (JAIST) EMM2012-102 |
There have recently been serious social issues involved in multimedia signal processing such as malicious attacks and ta... [more] |
EMM2012-102 pp.65-70 |
DC |
2012-06-22 13:00 |
Tokyo |
Room B3-1 Kikai-Shinko-Kaikan Bldg |
An evaluation of a don't care filling method to improve fault sensitization coverage Ryosuke Wakasugi, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyusyu Univ) DC2012-9 |
A single stuck-at fault model and a transition fault model have been widely used to generate test patterns for VLSIs. Ho... [more] |
DC2012-9 pp.1-6 |
NLP |
2012-03-28 15:40 |
Nagasaki |
Fukue Cultural Hall |
The detection of visuomotor adaptation in the game with time delayed response using electroencephalogram Shingo Iiyama, Kiyohisa Natsume (KIT) NLP2011-163 |
Human can adapt to the several changing environments. In the laboratory, the visuomotor adaptation is often studied. The... [more] |
NLP2011-163 pp.125-130 |
VLD |
2012-03-07 14:35 |
Oita |
B-con Plaza |
Performance of the Evaluation of a Variable-Latency-Circuit on FPGA Yuuta Ukon, Kenta Ando, Atsushi Takahashi (Osaka Univ) VLD2011-141 |
The performance of integrated circuits, which are the base of ICT nowaday,
is always requested to be improved.
In de f... [more] |
VLD2011-141 pp.127-132 |
DC |
2012-02-13 10:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Design of Dual Edge Triggered Flip-Flops and Application to Signal Delay Detection Yoshihiro Ohkawa, Yukiya Miura (TMU) DC2011-76 |
Conventional edge triggered flip-flops sample a data signal synchronizing with single clock edge. If a noise signal occu... [more] |
DC2011-76 pp.1-6 |
DC |
2012-02-13 11:05 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2011-78 |
In this paper, we present to generate a test vector set to detect both transition and path delay faults. The proposed me... [more] |
DC2011-78 pp.13-18 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:30 |
Miyazaki |
NewWelCity Miyazaki |
On the design for testability method using Time to Digital Converter for detecting delay faults Hiroyuki Makimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) VLD2011-84 DC2011-60 |
We propose the design for testability method for detecting delay fault that can form a TDC(Time-to-Digital Converter) to... [more] |
VLD2011-84 DC2011-60 pp.185-190 |
EMM |
2011-11-15 11:15 |
Miyagi |
|
Study on Reversible Watermarking for Digital Audio Based on Cochlear Delay Characteristics Masashi Unoki, Ryota Miyauchi (JAIST) EMM2011-50 |
There have recently been serious social issues involved in multimedia
signal processing such as digital rights manageme... [more] |
EMM2011-50 pp.59-64 |
MSS, CAS, VLD, SIP |
2011-07-01 14:30 |
Okinawa |
Okinawa-Ken-Seinen-Kaikan |
Performance Evaluation of Various Configurations of Adder in Error Detection/Correction Circuits Kenta Ando, Atsushi Takahashi (Osaka Univ.) CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 |
The performance of a circuit is improved by introducing error detection/correction mechanism which uses the variation of... [more] |
CAS2011-26 VLD2011-33 SIP2011-55 MSS2011-26 pp.147-152 |
VLD |
2011-03-04 13:10 |
Okinawa |
Okinawaken-Danjo-Kyodo-Sankaku Center |
An evaluation of error detection/correction circuits by gate level simulation Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) VLD2010-141 |
In a typical synchronous circuit design, the maximum delay between flip-flops gives a lower bound of the clock period su... [more] |
VLD2010-141 pp.147-152 |
DC |
2011-02-14 13:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Test Pattern Generation for Highly Accurate Delay Testing Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-64 |
We propose a new faster-than-at-speed test method to detect small delay defects. As semiconductor technology is scaling ... [more] |
DC2010-64 pp.33-38 |
US |
2010-09-29 17:05 |
Miyagi |
Tohoku Univ. |
Signal Delay Compensation on Fast Scanning Acoustic Wave Detection System Takeshi Itakura, Keisuke Kashiwa, Nan Wu, Tatsuya Omori, Ken-ya Hashimoto, Masatsune Yamaguchi (Chiba Univ.) US2010-57 |
This paper describes the enhancement of the measurement speed by delay time compensation caused in detection electronics... [more] |
US2010-57 pp.49-52 |
AN |
2010-07-15 14:10 |
Hokkaido |
Hakodate City Central Library |
DTN Routing for Mobile Nodes with Variable Speed Yo Chigira, Hiroaki Higaki (Tokyo Denki Univ.) AN2010-12 |
In an environment with sparse distribution of mobile wireless nodes, conventional wireless multihop ad-hoc routing proto... [more] |
AN2010-12 pp.13-18 |
EA |
2010-06-10 16:30 |
Hokkaido |
Health Sci. Univ. of Hokkaido |
A study on data hiding in speech signals using cochlear delay characteristics Masashi Unoki, Atsushi Haniu, Toshizou Kosugi, Ryota Miyauchi (JAIST) EA2010-27 |
This paper reports possibility of data hiding (speech watermarking) in
speech signals based on cochlear delay character... [more] |
EA2010-27 pp.31-36 |