IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 27 of 27 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
PRMU, HIP 2010-03-16
11:30		 Kagoshima Kagoshima Univ. Algorithms and Implementation of Cooperative Camera Network with DCOP
Shinya Kato, Toshihiro Matsui, Hiroshi Matsuo (Nagoya Inst. of Tech.) PRMU2009-296 HIP2009-181		 Distributed sensor network is an important research area of multi-agent
systems. We focus on a type of distributed sen... [more]		 PRMU2009-296 HIP2009-181
pp.371-376
MW 2010-03-05
11:10		 Kyoto Ryukoku Univ. Development of Low Power Ring-Type DCO for multi-standard wireless communication system
Satoshi Hamada, Abhishek Tomar, Ramesh Pokharel, Haruichi Kanaya, Keiji Yoshida (Kyushu Univ.) MW2009-204		 (To be available after the conference date) [more] MW2009-204
pp.141-146
MW 2009-11-20
09:25		 Kagoshima Tanegashima Development of 2/5GHz DUALBAND Digitally-Controlled LC-Oscillator
Kenta Uchida, Abishek Tomar, Ramesh Pokharel, Haruichi Kanaya, Keiji Yoshida (Kyushu Univ) MW2009-136		 This paper presents a design methodology and verification of a 2/5 GHz dual band digitally-controlled oscillator (DCO). ... [more] MW2009-136
pp.47-52
MW, SCE 2009-04-23
10:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Discussion on the method of the performance improvement of 5.2GHz-Band DCO
Kenta Uchida, Abhishek Tomar, Ramesh Pokharel, Haruichi Kanaya, Keiji Yoshida (Kyushu Univ) SCE2009-3 MW2009-3		 In this paper, we designed and measured the digitally controlled oscillator (DCO) and compared this DCO with the frequen... [more] SCE2009-3 MW2009-3
pp.11-16
ICD, ITE-IST 2008-10-24
12:30		 Hokkaido Hokkaido University All digital PLL with independent loop characteristic by using fine clock-period comparator
Yukinobu Makihara, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano (Hokkaido Univ.) ICD2008-87		 We proposed new architecture of phase-locked loop (PLL) by using clock-period comparison. For a digitally controlled PLL... [more] ICD2008-87
pp.165-170
SR 2007-07-27
16:55		 Kanagawa   Studies on the Phase Noise and Spurious Level Behavior of an All Digital Phase Locked Loop
Michael Zamrowski (Johannes Gutenberg Univ.), Tsuyoshi Terao, Kiyomichi Araki (Tokyo Inst. of Tech.) SR2007-45		 An All Digital Phase Locked Loop (ADPLL) was proposed being suitable for a CMOS processed system on one chip digital RF ... [more] SR2007-45
pp.157-162
NLP 2007-03-06
09:50		 Miyagi   Paralleled multi-step analog-to-digital converters
Takayuki Kabasawa, Aya Tanaka, Yusuke Matsuoka, Toshimichi Saito (Hosei Univ.) 		This paper studies basic dynamics of paralleled multi-step A/D converter.
First, we introduce a basic Sigma-Delta modu... [more]		 NLP2006-156
pp.13-16
 Results 21 - 27 of 27 [Previous]  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan