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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-06 14:15 |
Kagoshima | Advice : An application design environment for various parallel processing hardware Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.)  CPSY2014-165 DC2014-91 |
We propose an application design environment: Advice (application design environment for various parallel processing har... [more] | CPSY2014-165 DC2014-91 pp.19-24 |
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| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-29 18:00 |
Kanagawa | Hiyoshi Campus, Keio University | CF3: Test suite for arithmetic optimization of C compilers Yusuke Hibino, Nagisa Ishiura (KGU) VLD2014-130 CPSY2014-139 RECONF2014-63 |
This article presents a compiler test suite "CF3," which targets arithmetic optimization, especially constant folding, o... [more] | VLD2014-130 CPSY2014-139 RECONF2014-63 pp.117-122 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 11:30 |
Kanagawa | Hiyoshi Campus, Keio University | Detecting Missed Arithmetic Optimization Opportunities Using Random Testing of C Compilers Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2014-139 CPSY2014-148 RECONF2014-72 |
This article presents new methods of detecting missed arithmetic optimization opportunities of C compilers by random tes... [more] | VLD2014-139 CPSY2014-148 RECONF2014-72 pp.169-174 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 13:40 |
Kanagawa | Hiyoshi Campus, Keio University | Relaxing constraint conditions in parallelizing compiler based on a polyhedral model Toma Ogata, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.) VLD2014-142 CPSY2014-151 RECONF2014-75 |
Recently, it is general that computer has more than one processor inside and it is important to parallelize program to ... [more] | VLD2014-142 CPSY2014-151 RECONF2014-75 pp.187-192 |
| SS, IPSJ-SE | 2013-10-24 11:10 |
Ishikawa | Design and Implementation of a Framework for API-Based Language Extension via Rule-Based Rewriting utilizing COINS Takuya Shiode, Hideyuki Kawabata, Toshiaki Kitamura (Hiroshima City Univ.) SS2013-38 |
Although C language is quite simple, the language is useful enough to develop various kind of applications utilizing a v... [more] | SS2013-38 pp.13-18 |
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| RECONF | 2013-09-18 16:20 |
Ishikawa | Japan Advanced Institute of Science and Technology | A Power-Performance model for 3-D stencil computation on an FPGA accelerator Keisuke Dohi, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2013-23 |
This paper presents user space parameters and characteristics modeling of 3-D stencil computing on a stream-oriented FPG... [more] | RECONF2013-23 pp.19-24 |
| RECONF | 2013-05-21 11:00 |
Kochi | Kochi Prefectural Culture Hall | Performance model evaluation for 3-D stencil computation using a high-level synthesis tool Keisuke Dohi, Yoshihiro Nakamura, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2013-12 |
In this paper, we evaluate a performance model for heat spreading simulation on a MaxCompiler, a kind of high- -level s... [more] |
RECONF2013-12 pp.61-66 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 15:35 |
Kanagawa | Scaling the size of Expressions in Random Testing of Arithmetic Optimization of C Compilers Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2012-117 CPSY2012-66 RECONF2012-71 |
This paper presents an enhanced method of testing validity of arithmetic optimization of C compilers using random progra... [more] | VLD2012-117 CPSY2012-66 RECONF2012-71 pp.57-62 |
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| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 14:25 |
Kanagawa | Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) VLD2012-132 CPSY2012-81 RECONF2012-86 |
In this paper, we describe an implementation of a pupil detection using MaxCompiler which is a high-level synthesis fram... [more] | VLD2012-132 CPSY2012-81 RECONF2012-86 pp.147-152 |
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| SS | 2013-01-10 14:45 |
Okinawa | Design and Implementation of Compilers Constructed using COINS for Language Extensions using APIs Takuya Shiode, Hideyuki Kawabata, Toshiaki Kitamura (Hiroshima City Univ.) |
Although C language is quite simple, the language is useful enough to develop various kind of applications utilizing a ... [more] |
SS2012-49 pp.19-24 |
|
| CPSY | 2012-10-12 15:10 |
Hiroshima | Shared Data Management Scheme for Java Layer-Unified Coarse Grain Task Parallel Processing Yuuki Ochi, Akimasa Yoshida (Toho Univ.) CPSY2012-39 |
In parallel processing on multicore processors, the layer-unified coarse grain task parallel processing scheme, which ex... [more] | CPSY2012-39 pp.49-54 |
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| KBSE, SS | 2012-07-28 14:20 |
Hokkaido | Future University Hakodate | Global Load Instruction Aggregation Considering Dimensions of Arrays Yasunobu Sumikawa, Munehiro Takimoto (TUS) SS2012-29 KBSE2012-31 |
Most of modern processors have some much faster cache memories than a main memory, and therefore, it is important to hit... [more] | SS2012-29 KBSE2012-31 pp.115-119 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2012-03-02 15:15 |
Miyagi | Profiling-based Source to Source Compiler for GPGPU Atsushi Yumoto, Nobuhiko Sugino (Titech) CPSY2011-83 DC2011-87 |
A new profiling-based C to CUDA compiler for GPCPU is proposed in order to help developing higher performance GPGPU appl... [more] | CPSY2011-83 DC2011-87 pp.79-84 |
|
| ICM, CQ, NS (Joint) |
2011-11-11 15:10 |
Aomori | Hirosaki University | A few remarks of the Implementation model of Elemenet Management Systems in the point of view of Querry-based computational model Manabu Nishio (NTT) ICM2011-27 |
In our previous papers, we proposed the implementation method of the protocol conversion processing part in which it can... [more] | ICM2011-27 pp.43-48 |
| CPSY | 2011-10-21 10:40 |
Hyogo | Java Layer-Unified Coarse Grain Task Parallel Processing on Multicore Processors Akimasa Yoshida, Tomohiro Ozawa (Toho Univ.) CPSY2011-28 |
In parallel processing on multicore processors, the layer-unified coarse grain task parallel processing scheme, which ex... [more] | CPSY2011-28 pp.19-24 |
|
| COMP | 2011-04-22 09:30 |
Kyoto | Kyoto University | A construction method for non-left-recursive parsing expression grammars Shunichi Matsubara, Shojiro Ogawa, Marin J. Duerst (Aoyama Gakuin Univ.) COMP2011-1 |
Parsing expression grammars (PEGs) have recently been used to describe the syntax of artificial languages such as progra... [more] | COMP2011-1 pp.1-8 |
| VLD | 2011-03-03 10:20 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Implementation and Security Evaluation of DPA-Resistant DES Circuit utilizing Domino-RSL technique Katsuhiko Iwai, Kenji Kojima, Mitsuru Shiozaki, Syunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.) VLD2010-126 |
Some secure DPA-resistant techniques to protect from Side-Channel Attack such as Differential Power Analysis (DPA) have ... [more] | VLD2010-126 pp.57-62 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-17 15:05 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Acceleration of Regression Test of Compilers by Program Merging Kazushi Morimoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Yuki Uchiyama (K-OPT), Nobuyuki Hikichi (SRA, Inc) VLD2010-94 CPSY2010-49 RECONF2010-63 |
This article presents a method of accelerating regression test of compilers by merging programs in test suites. Testing ... [more] | VLD2010-94 CPSY2010-49 RECONF2010-63 pp.63-67 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 13:15 |
Fukuoka | Kyushu University | A case study of the effective value range analysis for Behavioral synthesis Kenji Tomonaga, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2010-32 |
The digital circuit becomes more complex and larger scale recently, and behavioral synthesis that use behavioral descri... [more] |
CPSY2010-32 pp.1-6 |
| MSS | 2010-01-21 13:25 |
Aichi | Toyota Central R&D Labs. | Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme Masafumi Onouchi, Keisuke Toyama, Toru Nojiri, Makoto Satoh (Hitachi), Masayoshi Mase, Jun Shirako (Waseda Univ.), Mikiko Sato (Tokyo Univ. of Agr and Tech.), Masashi Takada, Masayuki Ito (Renesas), Hiroyuki Mizuno (Hitachi), Mitaro Namiki (Tokyo Univ. of Agr and Tech.), Keiji Kimura, Hironori Kasahara (Waseda Univ.) CST2009-38 |
We developed a software-execution framework for scalable increase of execution speed and low-power consumption based on ... [more] | CST2009-38 pp.7-12 |
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