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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ)  ICD2014-82 CPSY2014-94 |
Demands for low energy microcontrollers which are used in sensor nodes have been increasing in recent years. Also most m... [more] | ICD2014-82 CPSY2014-94 p.43 |
| CS | 2014-11-07 09:00 |
Hokkaido | Shiretoko (Hokkaido) | Time to Hold (TTH), an Optimal Cache Replacement Policy for Video Delivery on CCN Haipeng Li, Hidenori Nakazato (Waseda Univ.) CS2014-65 |
In-network caching, one of the characteristics of Content Centric Networking (CCN), allows the contents to be cached alo... [more] | CS2014-65 pp.69-74 |
| CPSY, DC | 2014-04-25 15:15 |
Tokyo | A Hardware Cache Mechanism for Column-Oriented Databases Akihiko Hamada, Hiroki Matsutani (Keio Univ.) CPSY2014-5 DC2014-5 |
A column-oriented store is one of structured storages (NOSQLs), in which a variable number of columns can be stored for... [more] |
CPSY2014-5 DC2014-5 pp.21-26 |
|
| IN, IA (Joint) |
2013-12-20 09:20 |
Hiroshima | Hiroshima City Univ. | Cache Replacement Method using Round-Trip Time in Content-Centric Networking Kenji Yokota, Kohei Sugiyama, Atsushi Tagami (KDDI R&D Labs) IN2013-110 |
In this paper, we propose a cache replacement method using rout-trip time (RTT) in content-centric networking (CCN). CCN... [more] | IN2013-110 pp.65-70 |
| RCS, NS (Joint) |
2013-12-19 08:35 |
Kagawa | Sunport Hall Takamatsu | Study on CCN Based Disaster System Yo Na, Arifuzzaman Mohammad, Keping Yu, Takuro Sato (Waseda Univ.) NS2013-134 |
(To be available after the conference date) [more] | NS2013-134 pp.1-6 |
| NS, CQ, ICM, NV (Joint) |
2013-11-15 11:40 |
Nagasaki | Goto Islands | Constraint-Based Distribution Method of In-Network Guidance Information in Content-Oriented Network Masayuki Kakida, Yosuke Tanigawa, Hideki Tode (Osaka Prefecture Univ.) NS2013-126 |
Lately, network usage is dominated by content distribution, and hence, Content Oriented Network (CON) has attracted atte... [more] | NS2013-126 pp.61-66 |
| KBSE, SS | 2012-07-28 14:20 |
Hokkaido | Future University Hakodate | Global Load Instruction Aggregation Considering Dimensions of Arrays Yasunobu Sumikawa, Munehiro Takimoto (TUS) SS2012-29 KBSE2012-31 |
Most of modern processors have some much faster cache memories than a main memory, and therefore, it is important to hit... [more] | SS2012-29 KBSE2012-31 pp.115-119 |
| VLD | 2011-03-02 14:00 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-118 |
In hierarchical cache configurations, L1 cache uses LRU as cache replacement policy but L2 and/or L3 caches use FIFO du... [more] |
VLD2010-118 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 09:30 |
Fukuoka | Kyushu University | Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-64 DC2010-31 |
The number of sets, block size and associativity determine processor's cache configuration. Particularly in embedded sys... [more] | VLD2010-64 DC2010-31 pp.55-60 |
| RCS, AN, MoNA, SR (Joint) |
2010-03-05 14:00 |
Kanagawa | YRP | Overlay and Clean Slate Technologies for Opportunistic Wireless Environments Ryoichi Shinkuma (Kyoto Univ.) RCS2009-318 MoMuC2009-91 SR2009-115 AN2009-84 |
Wireless access has been diversified; experienced transmission speed in wireless access dynamically changes depending on... [more] | RCS2009-318 MoMuC2009-91 SR2009-115 AN2009-84 pp.351-356(RCS), pp.101-106(MoMuC), pp.161-166(SR), pp.89-94(AN) |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 15:40 |
Kochi | Kochi City Culture-Plaza | Two-level Cache Simulation with L2 Unified Cache for Embedded Applications Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2009-47 DC2009-34 |
In this paper, we propose a two-level cache simulation method with L2 unified cache for embedded applications. It simula... [more] | VLD2009-47 DC2009-34 pp.37-42 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2009-03-05 15:45 |
Niigata | Sado Island Integrated Development Center | Single-Cycle-Accessible Two-Level Cache Architecture Seiichiro Yamaguchi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.) CPSY2008-91 DC2008-82 |
A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the ener... [more] | CPSY2008-91 DC2008-82 pp.19-24 |
| ICD, IPSJ-ARC | 2007-05-31 13:15 |
Kanagawa | Effect of Data Prefetching on Chip MultiProcessor Naoto Fukumoto, Tomonobu Mihara, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) |
Chip MultiProcessors (or CMPs) can achieve higher performance by means of exploiting thread level parallelism. Increasin... [more] | ICD2007-20 pp.19-24 |
|
| RECONF | 2005-05-12 11:00 |
Kyoto | Kyoto University | Implementation of an SMT Processor and its Reconfigurable Cache with FPGA Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo (Tokyo University of Agriculture and Technology) |
Recently, it becomes possible to implement a large-scale processor due to speed-up and large-scale integrity of an FPG... [more] |
RECONF2005-4 pp.19-24 |
| KBSE, JSAI-KBS | 2005-01-24 14:30 |
Kanagawa | Keio University | Random is better than LRU ? Kenichi Yoshida (U.Tsukuba), Masato Tsuru (kyutech), Satoshi Katsuno (kddilabs) |
In this paper, we propose a cache-based frequent item finding approach. By analyzing the characteristics of the proposed... [more] | KBSE2004-30 pp.37-41 |
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