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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-30 10:45 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter Shoma Ito, Daishi Nishiguchi, Masaaki Fukuhara (Tokai Univ.)  VLD2022-45 ICD2022-62 DC2022-61 RECONF2022-68 |
Logic elements of FPGA generally use Look-Up Table (LUT) circuits, and the most common types of LUT are 4-input and 6-in... [more] | VLD2022-45 ICD2022-62 DC2022-61 RECONF2022-68 pp.150-155 |
| ICD, SDM, ITE-IST [detail] | 2020-08-07 11:00 |
Online | Online | CMOS Inverter Transfer Characteristics on Steep SS “PN-Body Tied SOI-FET” Shota Ishiguro, Jiro Ida, Takayuki Mori (KIT), Koichiro Ishibashi (UEC) SDM2020-8 ICD2020-8 |
In this study, we report the CMOS Inverter Transfer Characteristics on Steep SS “PN-Body Tied SOI-FET” proposed in our l... [more] | SDM2020-8 ICD2020-8 pp.37-40 |
| ICD, CPSY, CAS | 2017-12-14 15:10 |
Okinawa | Art Hotel Ishigakijima | A 190mV Start-up Voltage Doubler Charge Pump with CMOS Gate Boosting Scheme using 0.18um Standard CMOS Process for Energy Harvesting Minori Yoshida, Kousuke Miyaji (Shinshu Univ.) CAS2017-91 ICD2017-79 CPSY2017-88 |
Recently, energy harvesting power supply circuit using a cold-start function for IoT devices is required to restore powe... [more] | CAS2017-91 ICD2017-79 CPSY2017-88 p.127 |
| SDM | 2017-02-06 13:35 |
Tokyo | Tokyo Univ. | [Invited Talk]
Electrical coupling of stacked transistors in monolithic three-dimensional inverters and its dependence on the interlayer dielectric thickness Junichi Hattori, Koichi Fukuda, Toshifumi Irisawa, Hiroyuki Ota, Tatsuro Maeda (AIST) SDM2016-143 |
We study the electrical coupling of stacked transistors in monolithic three-dimensional (3D) inverters and investigate i... [more] | SDM2016-143 pp.23-28 |
| ICD, SDM | 2014-08-05 13:05 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | [Invited Talk]
Oxide Semiconductor-based Transistors Formed in LSI Interconnects Hiroshi Sunamura, Naoya Furutake, Shinobu Saito, Mitsuru Narihiro, Yoshihiro Hayashi (REL) SDM2014-76 ICD2014-45 |
We report on the latest progress on our proposed new transistor technology called BEOL-FET, in which we form oxide-based... [more] | SDM2014-76 ICD2014-45 pp.77-82 |
| ED | 2014-04-18 09:00 |
Yamagata | The 100th Anniversary Hall, Yamagata University | Fabrication of Fully Solution-processed Organic Thin-Film Transistor and Application to Integrated Circuits Yasunori Takeda, Yu Kobayashi (Yamagata Univ.), Faiz Adi Ezarudin Bin Adib (SATO HOLDINGS), Kenjiro Fukuda, Daisuke Kumaki, Shizuo Tokito (Yamagata Univ.) ED2014-11 |
Organic Thin Film Transistor (OTFT) is very attractive for a varied range of applications such as flexible display, and ... [more] | ED2014-11 pp.41-45 |
| OME | 2011-12-21 15:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Low Operation Voltage Organic Transistors on Shape-Memory Film with Planarization Yu Kato (Univ. of Tokyo), Tsuyoshi Sekitani (Univ. of Tokyo/JST), Tomoyuki Yokota, Kazunori Kuribara (Univ. of Tokyo), Ute Zschieschang, Hagen Klauk (Max Planck Inst.), Tatsuya Yamamoto, Kazuo Takimiya (Hiroshima Univ.), Masaaki Ikeda, Hirokazu Kuwabara (Nippon Kayaku), Takao Someya (Univ. of Tokyo/JST) OME2011-70 |
We fabricated low operation voltage organic transistors on shape-memory film which memorizes its shape by applying heat ... [more] | OME2011-70 pp.23-28 |
| CAS, NLP | 2011-10-20 14:20 |
Shizuoka | Shizuoka Univ. | Fast Simulation of Multiconductor System with Nonlinear Devices by Using Block-Latency Insertion Method and Reduced Order Model Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2011-41 NLP2011-68 |
This paper describes a fast circuit simulation technique based on the block-latency insertion method (block-LIM) and a m... [more] | CAS2011-41 NLP2011-68 pp.49-54 |
| SDM, ICD | 2011-08-25 10:25 |
Toyama | Toyama kenminkaikan | Power-Performance Estimation of Datta-Das Spin Transistor Yoshiyuki Kondo, Shigeru Kawanaka, Kanna Adachi (Toshiba) SDM2011-74 ICD2011-42 |
We report the results of power-performance analysis of Datta-Das spin transistor(SFET) in this paper. We clarified it... [more] |
SDM2011-74 ICD2011-42 pp.17-22 |
| ICD, ITE-IST | 2011-07-22 17:25 |
Hiroshima | Hiroshima Institute of Technology | High Speed LED Driver for Visible Light Communications with Drawing Remaining Carrier out by CMOS Inverter. Toshiki Kishi, Hiroyuki Tanaka, Yohtaro Umeda (TUS) ICD2011-38 |
The visible light communications that communicates by modulating the light of illumination, which is the existing infras... [more] | ICD2011-38 pp.137-142 |
| ICD, ITE-IST | 2010-07-23 10:05 |
Osaka | Josho Gakuen Osaka Center | Considerations of a Common-mode Feedback Circuit in the CMOS Inverter-based Differential Amplifier. Masayuki Uno (Linear Cell Design) ICD2010-32 |
Push-pull CMOS inverter is effective for high-speed, low-power operations, but it has poor CMRR and PSRR characteristics... [more] | ICD2010-32 pp.67-72 |
| ED, SDM | 2010-07-02 12:00 |
Tokyo | Tokyo Inst. of Tech. Ookayama Campus | The Analysis of Temperature Dependency of the Mobility In High-k/Metal Gate MOSFET and the Performance on its CMOS Inverter Takeshi Sasaki, Takuya Imamoto, Tetsuo Endoh (Tohoku Univ.) ED2010-92 SDM2010-93 |
As the integration density and capacitance of semiconductor devices have increased, high-dielectric (High-k) materials h... [more] | ED2010-92 SDM2010-93 pp.177-182 |
| OME | 2010-05-27 13:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | CMOS Inverter Based on a Stacked Structure Using Silicone-Resin as Dielectric Layers Kodai Kikuchi, Hiroshi Yamauchi, Masaaki Iizuka, Masatoshi Sakai, Masakazu Nakamura, Kazuhiro Kudo (Chiba Univ.) OME2010-18 |
We have demonstrated the inverter operation of stacked-structure CMOS devices using pentacene and ZnO as active layers. ... [more] | OME2010-18 pp.7-10 |
| VLD | 2010-03-10 15:25 |
Okinawa | Generation Mechanism of SEU and MCU Caused by Parasitic Lateral Bipolar Transitstors Chikara Hamanaka (Kyoto Institute of Tech.), Jun Furuta, Hiroaki Makino (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Institute of Tech.), Hidetoshi Onodera (Kyoto Univ./JST, CREST) VLD2009-103 |
Tolerance for soft-error decreases as integration advances. SEU(Single Event Upset), flipping one bit and MCU(Multi-Cel... [more] |
VLD2009-103 pp.25-30 |
|
| ED, SDM | 2010-02-23 10:10 |
Okinawa | Okinawaken-Seinen-Kaikan | CMOS inverters based on carbon nanotube field-effect transistors with SiNx passivation films Takaomi Kishimoto, Yasuhide Ohno, Kenzo Maehashi, Koichi Inoue, Kazuhiko Matsumoto (ISIR, Osaka Univ.) ED2009-206 SDM2009-203 |
We have demonstrated logic gates based on complementary carbon nanotube field-effect transistors (CNT-FETs) with SiNx pa... [more] | ED2009-206 SDM2009-203 pp.59-63 |
| EMD | 2009-03-06 15:50 |
Tokyo | Kougakuin Univ. | Simulation study of analog input buffer characteristics in CMOS integrated circuits Yuuto Horiki, Keiko Fukuda (Tokyo Metropolitan Coll. of Ind Tech.) EMD2008-144 |
Complementary-type analog input buffer is proposed for low-voltage operation in CMOS integrated circuits. It consists o... [more] | EMD2008-144 pp.41-44 |
| SDM | 2008-10-10 14:30 |
Miyagi | Tohoku Univ. | Impact of Fully Depleted Silicon-On-Insulator Accumualation-mode CMOS on Si(110) Ching Foa Tye, Weitao Cheng, Akinobu Teramoto, Shigetoshi Sugawa, Tadahiro Ohmi (Tohoku Univ.) SDM2008-164 |
This paper demonstrates the characteristic of Accumulation-mode Fully Depleted Silicon-On-Insulator (Acc-FD-SOI) MOSFETs... [more] | SDM2008-164 pp.51-56 |
| ICD, SDM | 2007-08-24 08:30 |
Hokkaido | Kitami Institute of Technology | A Very Wideband Fully Balanced Active RC Polyphase Filter Based on CMOS Inverters in 0.18μm CMOS Technology Keishi Komoriyama, Eiich Yoshida, Makoto Yashiki, Hiroshi Tanimoto (Kitami Inst. Tech.) SDM2007-155 ICD2007-83 |
A very wideband active RC polyphase filter(RCPF) is presented. It can expand image-rejection band of passive RCPF. To ... [more] |
SDM2007-155 ICD2007-83 pp.79-84 |
| CAS, SIP, VLD | 2007-06-22 10:30 |
Hokkaido | Hokkaido Tokai Univ. （Sapporo) | A Lateral Unified-CBiCMOS Buffer Circuit for Driving 5nF Maximum Load Capacitance per CCD Clock Masatoshi Kobayashi, Takashi Hamahata, Toshiro Akino, Kenji Nishi, Cuong Vo Le, Kousei Takehara, T. Goji Etoh (Kinki Univ.) CAS2007-22 VLD2007-38 SIP2007-52 |
Since 2001, we have been developing an in-situ storage image sensor (ISIS) that captures 100 to 150 consecutive images a... [more] | CAS2007-22 VLD2007-38 SIP2007-52 pp.19-24 |
| EMCJ | 2006-09-01 14:25 |
Osaka | Osaka Univ. | Equivalent circuit reduction of CMOS output buffer for high speed simulation of power supply noise Junya Yamamoto, Osami Wada, Takashi Hisakado (Kyoto Univ.) EMCJ2006-46 |
To realize high-speed noise simulation at board level, an output buffer model of a CMOS inverter circuit is simplified a... [more] | EMCJ2006-46 pp.13-17 |
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