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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SITE, IA, IPSJ-IOT [detail] | 2021-03-02 13:55 |
Online | Online | Mutual Secrecy of Attributes and Authorization Policies in Identity Federation Satsuki Nishioka, Yasuo Okabe (Kyoto Univ.)  SITE2020-53 IA2020-49 |
In modern Web services, authentication federation that separates the Identity Provider (IdP), which centrally manages au... [more] | SITE2020-53 IA2020-49 pp.93-100 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 14:25 |
Online | Online | Variable Ordering for Minimizing Power Consumption of BDD-based Optical Logic Circuits Ryosuke Matsuo, Shin-ichi Minato (Kyoto Univ) VLD2020-24 ICD2020-44 DC2020-44 RECONF2020-43 |
Optical logic circuits based on integrated nanophotonics have attracted significant interest due to their ultra-high-spe... [more] | VLD2020-24 ICD2020-44 DC2020-44 RECONF2020-43 pp.78-83 |
| RECONF | 2020-09-11 15:35 |
Online | Online | Inductive Invariant Generation Based on Binary Decision Diagram and its Application to Logic Synthesis Liu ZiHao, Miyasaka Yukio, Fujita Masahiro (UT) RECONF2020-28 |
In this paper, we mainly focus on inductive invariant generation using binary decision diagram (BDD), and its applicatio... [more] | RECONF2020-28 pp.54-59 |
| NS, IN (Joint) |
2016-03-04 09:30 |
Miyazaki | Phoenix Seagaia Resort | Evaluating connectivity on physical networks with switch failures Koki Sonoda, Jun Kawahara (NAIST), Takeru Inoue (NTT), Shoji Kasahara (NAIST), Osamu Akashi, Ryoichi Kawahara, Hiroshi Saito (NTT) NS2015-213 |
In a network reliability evaluation, it is a problem to compute the probability that two specified nodes can communicate... [more] | NS2015-213 pp.261-266 |
| COMP | 2015-12-01 10:30 |
Osaka | A Fast Method for Solving Constrained Shortest Path Problems on Directed Acyclic Graphs Fumito Takeuchi (Hokkaido Univ.), Masaaki Nishino (NTT), Norihito Yasuda (Hokkaido Univ.), Takuya Akiba (NII), Shin-ichi Minato (Hokkaido Univ.), Masaaki Nagata (NTT) COMP2015-31 |
This paper deals with shortest path problems on directed acyclic graphs (DAGs), under logical constraints posed between... [more] | COMP2015-31 pp.9-16 |
|
| QIT (2nd) |
2013-11-18 11:20 |
Tokyo | Waseda Univ. | A Representation of Quantum Graph States Using Binary Decision Diagrams Yuto Hirakuri, Hidefumi Hiraishi, Hiroshi Imai (Univ. of Tokyo) |
We discuss an efficient classical simulation of measurement-based quantum computation (MQC), focusing on relationships b... [more] | |
| COMP | 2013-03-18 13:45 |
Gifu | Gifu University | Compact and Fast Indices Based on Zero-Suppressed Binary Decision Diagrams Shuhei Denzumi (Hokkaido Univ.), Jun Kawahara (NAIST), Koji Tsuda (AIST/JST), Hiroki Arimura (Hokkaido Univ.), Shin-ichi Minato (Hokkaido Univ./JST), Kunihiko Sadakane (NII) COMP2012-56 |
In many real-life problems, we are often faced with manipulating families of sets. Manipulation of large-scale set famil... [more] | COMP2012-56 pp.23-30 |
| ED, SDM | 2010-02-23 11:00 |
Okinawa | Okinawaken-Seinen-Kaikan | Compact Reconfigurable BDD Logic Circuits utilizing GaAs Nanowire Network Yuta Shiratori, Kensuke Miura (Hokkaido Univ.), Seiya Kasai (Hokkaido Univ./JST) ED2009-208 SDM2009-205 |
We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon’s expansion of Boolean logic functio... [more] | ED2009-208 SDM2009-205 pp.71-76 |
| SDM, ED | 2008-07-10 10:00 |
Hokkaido | Kaderu２・７ | 2-bit Arithmetic Logic Unit Utilizing Hexagonal BDD Architecture for Implemention of Nanoprocessor on GaAs Nanowire Network Hong-Quan Zhao (Hokkaido Univ.), Seiya Kasai (Hokkaido Univ./JST), Tamotsu Hashizume (Hokkaido Univ.) ED2008-66 SDM2008-85 |
2-bit arithmetic logic unit (ALU) utilizing the binary-decision diagram (BDD) logic architecture for nanoprocessor is fa... [more] | ED2008-66 SDM2008-85 pp.139-144 |
| AI | 2007-05-31 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Recent Topics on Data Mining and Knoledge Discovery Using Binary Decision Diagrams Shin-ichi Minato (Hokkaido Univ.) AI2007-6 |
Binary Decision Diagrams (BDDs) are the efficient data structure for representing Boolean functions on the main memory. ... [more] | AI2007-6 pp.27-32 |
| SCE | 2004-10-22 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Advanced Design Approaches for SFQ Logic Circuits based on the Binary Decision Diagram Takanobu Nishigai, Maki Ito, Nobuyuki Yoshikawa (Yokohama National Univ.), Koji Obata, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) |
We have been developing a design methodology of SFQ logic circuits based on the binary decision diagram(BDD). In the pre... [more] | SCE2004-27 pp.13-18 |
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