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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2010-03-11 16:05 |
Okinawa | Evaluation of a Detail Via Arrangement Method for 2-Layer Ball Grid Array Packages Masaki Kinoshita (Tokyo Inst. of Tech.), Yoichi Tomioka (Tokyo Univ. of Agr and Tech.), Atsushi Takahashi (Osaka Univ.)  VLD2009-117 |
It takes a lot of time to obtain a routing design of the ball grid array (BGA) package which is one of LSI package, sinc... [more] | VLD2009-117 pp.109-114 |
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| VLD | 2009-09-24 13:55 |
Osaka | Osaka University | A Detail Via Arrangement Method for Reduction of Wire Congestion in 2-Layer Ball Grid Array Packages Masaki Kinoshita, Yoichi Tomioka (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.) VLD2009-30 |
A BGA package realizes a lot of connections between a chip and a printed board. The quality of routing design obtained ... [more] |
VLD2009-30 pp.7-12 |
| VLD, ICD | 2008-03-06 16:10 |
Okinawa | TiRuRu | Global Routing Method of Plating Lead for 2-Layer BGA Packages Naoki Sato, Yoichi Tomioka, Atsushi Takahashi (Tokyo Tech) VLD2007-154 ICD2007-177 |
In this paper, we propose a global routing method for 2-layer BGA packages in which the layer assignment of plating le... [more] |
VLD2007-154 ICD2007-177 pp.61-66 |
| ICD, VLD | 2007-03-08 13:50 |
Okinawa | Mielparque Okinawa | BGA Routing by The Potential Router Takayuki Hiromatsu, Masato Inagi, Yasuhiro Takashima, Yoji Kajitani (Univ. of Kitakyushu) |
As the number of devices in an LSI chip becomes larger, the number of package pins also becomes larger. To fold the pins... [more] | VLD2006-131 ICD2006-222 pp.73-78 |
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