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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| COMP, IPSJ-AL | 2024-05-09 10:45 |
Kyoto | Kyoto University (Rakuyu-kaikan) | Depth-Three Circuits for Inner Product and Majority Functions Kazuyuki Amano (Gunma Univ.) |
(To be available after the conference date) [more] | |
| ICTSSL, CAS | 2024-01-25 13:15 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Talk]
Integrated circuits and digital calibration for high-speed high-resolution low-power A/D converters Takashi Oshima (Hitachi)  CAS2023-89 ICTSSL2023-42 |
Given rapid advance of AI, acquisition of high-quality digital data from analog sensor signals is crucial than ever. A h... [more] | CAS2023-89 ICTSSL2023-42 pp.34-39 |
| EE, IEE-SPC, IEE-EDD (Joint) |
2017-11-21 10:45 |
Kagoshima | Kagoshima Univ. | Experimental Verification of Current Sensorless ZVS Assist Control Based on Voltage Transition Waveform Masaya Takahashi, Nobuhisa Yamaguchi, Eisuke Takahashi, Kazuyoshi Obayashi (DENSO), Kimihiro Nishijima (Oita Univ.) EE2017-41 |
The main cause of an efficiency degradation in a DC to DC converter is a switching loss. ZVS assist circuit is known as ... [more] | EE2017-41 pp.33-38 |
| ICD, SDM, ITE-IST [detail] | 2016-08-02 09:45 |
Osaka | Central Electric Club | [Invited Talk]
CMOS Analog IC Technologies Toward AI Era Toshimasa Matsuoka (Osaka Univ.) SDM2016-55 ICD2016-23 |
Some techniques for improvement of a RF transmitter IC with genetic algorithm, error correction of an A/D converter wi... [more] |
SDM2016-55 ICD2016-23 pp.59-61 |
| SDM | 2015-01-27 15:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM Macros with Wordline Overdriven Assist Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Miki Tanaka, Koji Nii (Renesas) SDM2014-144 |
We demonstrate 16 nm FinFET High-k/Metal-gate SRAM macros with a wordline (WL) overdriven read/write-assist circuit. Tes... [more] | SDM2014-144 pp.37-40 |
| ICD | 2012-12-18 13:30 |
Tokyo | Tokyo Tech Front | [Invited Talk]
CMOS analog mixed circuit and its applications Shouhei Kousai (Toshiba) ICD2012-118 |
Recent CMOS Analog VLSI has evolved with CMOS Digital circuits and has been enabled various and ubiquitous applications.... [more] | ICD2012-118 pp.115-120 |
| VLD | 2010-09-27 16:30 |
Kyoto | Kyoto Institute of Technology | [Invited Talk]
An Automatic Test Generation Framework for Digitally-Assisted Analog Circuit Satoshi Komatsu, Mohamed Abbas (Univ. of Tokyo), Yasuo Furukawa (Advantest), Kunihiro Asada (Univ. of Tokyo) VLD2010-46 |
This paper presents a new analog ATPG (AATPG) framework that generates near-optimal test stimulus for the digitally-assi... [more] | VLD2010-46 pp.25-30 |
| ICD, ITE-IST | 2010-07-22 14:00 |
Osaka | Josho Gakuen Osaka Center | [Invited Talk]
Digitally-Assisted Analog Test Technology
-- Analog Circuit Test Technology in Nano-CMOS Era -- Haruo Kobayashi, Takahiro J. Yamaguchi (Gunma Univ.) ICD2010-27 |
This paper reviews current production testing issues for analog and mixed-signal SoC, and discusses the following: (i)... [more] |
ICD2010-27 pp.37-42 |
| ICD | 2010-04-22 10:50 |
Kanagawa | Shonan Institute of Tech. | A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Yasunobu Nakase, Hirofumi Shinohara (Renesas Electronics) ICD2010-3 |
We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. ... [more] | ICD2010-3 pp.13-16 |
| SDM [detail] | 2008-11-14 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
[Invited]Robust Design of Embedded SRAM on Deep-submicron Technology Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Hirofumi Shinohara (Renesas Technology Corp.) SDM2008-178 |
We develop high-density SRAM module in deep-submicron CMOS technology with the variation tolerant assist circuits agains... [more] | SDM2008-178 pp.55-60 |
| ICD, SDM | 2008-07-17 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka (Renesas Tech.), Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Katsuji Satomi, Hironori Akamatsu (Matsushita Elec.), Hirofumi Shinohara (Renesas Tech.) SDM2008-131 ICD2008-41 |
We develop 512 Kb SRAM module in 45 nm LSTP CMOS technology with the variation tolerant assist circuits against process ... [more] | SDM2008-131 ICD2008-41 pp.17-22 |
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