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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MW (2nd) |
2018-06-27 - 2018-06-29 |
Overseas | KMITL, Bangkok, Thailand | Design of Multi-Section LC-Ladder Divider at VHF-Band Kensuke Nagano, Tadashi Kawai, Akira Enokihara (Univ. of Hyogo) |
This paper describes a broadband lumped-element power divider composed of multi-section LC-ladder circuits and an isolat... [more] | |
| SIS | 2017-12-15 10:00 |
Tottori | Tottori Prefectural Center for Lifelong Learning | Elimination of high radioactivity data using forward-projection technique in myocardial perfusion SPECT image Jo Mitsuzuka, Kazuhiro Sawa, Satoru Kishida (Tottori Univ.)  SIS2017-48 |
Our purpose is to eliminate a high radioactivity data such as a gall bladder, in the projection data to reduce artifacts... [more] | SIS2017-48 pp.85-87 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 11:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Implementation and Optimization of Parallel Prefix Adder Using Majority Function Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2017-46 DC2017-52 |
In recent FPGAs and post CMOS devices, three-input majority operation can be efficiently realized and circuit configuration... [more] | VLD2017-46 DC2017-52 pp.109-114 |
| SDM, ED, CPM | 2017-05-25 15:50 |
Aichi | VBL, Nagoya University | Development of Plasmonic Logical Circuit Using Multimode Interference Ryo Watanabe, Masashi Ota, Yudai Kikuchi, Tomohiro Hirano, Yuya Ishii, Mitsuo Fukuda (TUT) ED2017-20 CPM2017-6 SDM2017-14 |
Logic circuits using Surface Plasmon Polaritons(SPPs) as signal carriers have been attracting attentions. Recently, we h... [more] | ED2017-20 CPM2017-6 SDM2017-14 pp.29-32 |
| VLD | 2017-03-03 11:20 |
Okinawa | Okinawa Seinen Kaikan | Optimization of Parallel Prefix Adder Using Simulated Annealing Takayuki Moto, Mineo Kaneko (JAIST) VLD2016-127 |
In this report, simulated annealing based optimization of parallel prefix adders (PPA) is proposed. In order to construc... [more] | VLD2016-127 pp.139-144 |
| MI | 2017-01-18 14:15 |
Okinawa | Tenbusu Naha | MI2016-87 |
(To be available after the conference date) [more] | MI2016-87 pp.63-64 |
| MW | 2016-12-15 15:10 |
Kanagawa | National Defense Academy | Design method of unequal Wilkinson power divider using LC-ladder circuits Yosuke Okada, Tadashi Kawai, Akira Enokihara (Univ. of Hyogo) MW2016-146 |
Authors have proposed the Wilkinson power divider using LC-ladder circuits for miniaturization of conventional power div... [more] | MW2016-146 pp.79-82 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 15:00 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Easily-testable Carry Select Adder with Online Error Detection Capability Nobutaka Kito (Chukyo Univ.) VLD2015-72 DC2015-68 |
An easily testable multi-block carry select adder with online error detection capability is proposed. An easily testable... [more] | VLD2015-72 DC2015-68 pp.225-230 |
| WIT | 2015-08-26 09:45 |
Nagano | Shinshu University Faculty of Engineering | Effect for Quality Improvement of Wound Ostomy and Continence Nursing Using a Diagnostic Ultrasound Imaging System for the Bladder Emi Ozawa, Hirohumi Ymaguti (Showa inan), Manabu Chikai, Shuichi Ino (AIST) WIT2015-44 |
In our hospital, inpatients of the elderly people exceed 60 %, and we make the excretion care for the importance on thei... [more] | WIT2015-44 pp.43-46 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-75 |
In recent years, high speed and high precision computing is increasingly needed. Hardware support for IEEE754 compliant... [more] |
CPSY2014-75 pp.19-23 |
| MW | 2013-12-19 11:50 |
Saitama | Saitama Univ. | Experimental parameter extraction method for an equivalent multistage thermal RC ladder circuit used to a GaN HEMT large-signal model Shingo Yoshida, Ryo Ishikawa, Kazuhiko Honjo (UEC) MW2013-156 |
We have been developing an analysis method for third-order intermodulation distortion caused by a thermal memory effect.... [more] | MW2013-156 pp.29-34 |
| SDM | 2013-12-13 11:20 |
Nara | NAIST | Design and development of Gate Array using Poly-Si TFT Masashi Inoue, Tokiyoshi Matsuda, Mutsumi Kimura (Ryukoku Univ.) SDM2013-123 |
In this study, we performed the design and development of gate arrays using poly-Si TFTs. We designed and evaluated the... [more] | SDM2013-123 pp.43-47 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 08:50 |
Kagoshima | Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC Wataru Yoshimura, Kenichi Ohhata (Kagoshima Univ.) CPM2013-108 ICD2013-85 |
A resistor ladder is an important circuit block for the parallel architecture analog-to-digital converters (ADCs). The o... [more] | CPM2013-108 ICD2013-85 pp.1-6 |
|
| MW | 2013-11-21 11:15 |
Kagoshima | Kagoshima Prefectural Culture Center | Spiral Inductor One-port Equivalent Circuits Analysis with the Oscillator’s Q-Factor Formulation
-- Calculation Results of Various Q-Factor -- Yoshitada Iyama (Kumamoto Natl.Col.of Tech.) MW2013-134 |
Active Q-factor formulas for one-port equivalent circuits of spiral inductor have been derived. The results have been c... [more] | MW2013-134 pp.17-21 |
| SCE | 2013-07-22 10:40 |
Tokyo | Kikaishinkou-kaikan Bldg. | Design and evaluation of the 2-bit Bit-Slice Adder based on 10kA/cm^2 process Kensuke Takata, Yuhi Hayakawa, Masamitsu Tanaka, Akira Fujimaki (Nagoya Univ.) SCE2013-12 |
A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively.... [more] | SCE2013-12 pp.11-16 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2013-03-14 15:05 |
Nagasaki | Self-Checking Carry Look-ahead Adder by Carry-bit Duplication Akihiro Mitoma (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) CPSY2012-98 DC2012-104 |
We propose a self-checking carry look-ahead adder, which can detect errors caused by a single stuck-at fault in the adde... [more] | CPSY2012-98 DC2012-104 pp.277-282 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 13:25 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Analytical model of energy dissipation for comparing adder architectures Nao Konishi, Kimiyoshi Usami (Shibaura I.T.) VLD2012-80 DC2012-46 |
This paper describes analytical models for delay and energy dissipation of ripple-carry, carry look-ahead, and parallel ... [more] | VLD2012-80 DC2012-46 pp.123-128 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 16:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Design Method of Fault-Secure Parallel Prefix Adders by Carry-Bit Duplication Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) VLD2012-106 DC2012-72 |
We show a design method of fault-secure parallel prefix adders with various prefix structures. Adders by the method gen... [more] |
VLD2012-106 DC2012-72 pp.273-278 |
| MW | 2012-11-22 09:00 |
Okinawa | Spiral Inductor Equivalent Circuits Analysis with the Oscillator's Q-Factor Formulation Yoshitada Iyama (Kumamoto National College of Technology) MW2012-118 |
Active Q-factor formulas for spiral inductors have been derived. They are described as a function of equivalent circuit ... [more] | MW2012-118 pp.29-34 |
|
| US | 2012-08-28 15:00 |
Overseas | Pukyong National University | Target strength pattern measurement of juvenile chum salmon (Oncorhynchus keta) in a tank by the controlled method Kouichi Sawada, Tomohiko Matsuura, Hideaki Aono (Fisheries Research Agency), Akihiko Hashiba (Sanriku-Yamada Fisheries Cooperative) US2012-55 |
Target strengths of juvenile chum salmons ($\textit{Oncorhynchus keta}$), standard body length=40.2 - 51.3 mm) from side... [more] | US2012-55 pp.105-110 |
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