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 Results 21 - 26 of 26 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2009-06-19
11:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Diagnositc Test Generation for Transition Faults Using a Stuck-at ATPG Tool
Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi (Ehime Univ.), Yoshihiro Simizu, Takashi Aikyo (STARC), Yuzo Takamatsu (Ehime Univ.) DC2009-13		 In modern high-speed LSIs, defects that cause timing failure occur often, and thus their detection and diagnosis are get... [more] DC2009-13
pp.19-24
DC 2009-02-16
10:50		 Tokyo   On the Acceleration of Redundancy Identification for Hard-to-ATPG faults Using SAT
Yusuke Akiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) DC2008-70		 Recently, 100% Fault coverage required in VLSI testing. However, ATPG algorithms can not classify all hard-to-test fault... [more] DC2008-70
pp.13-18
ISEC 2008-05-16
13:00		 Tokyo Kikai-Shinko-Kaikan Bldg. Reconsideration of Algorithmic Tamper Proof Devices using PIN (part 2)
Yuichi Komano (Toshiba), Kazuo Ohta (UEC), Hideyuki Miyake, Atsushi Shimbo (Toshiba) ISEC2008-7		 Gennaro et al.~discussed the algorithmic tamper proof (ATP) devices using the personal identification number (PIN); and ... [more] ISEC2008-7
pp.43-48
DC 2008-02-08
16:05		 Tokyo Kikai-Shinko-Kaikan Bldg. Current dissipation of Test pattern generators using ATPG vectors
Hidekazu Tsuchiya, Takaya Abe, Takeshi Asakawa (Tokai univ.) DC2007-80		 Recently, the operating speed of LSI is more fast and the scale of LSI is more larger. These induce increasing the dissi... [more] DC2007-80
pp.83-88
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-20
10:30		 Fukuoka Kitakyushu International Conference Center A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing
Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT) VLD2007-71 DC2007-26		 High power dissipation can occur when a response to the test vector is captured by flip-flops in at-speed scan testing, ... [more] VLD2007-71 DC2007-26
pp.7-12
ICD, CPM 2007-01-19
13:00		 Tokyo Kika-Shinko-Kaikan Bldg. A Constrained Test Generation Method for Low Power Testing
Yoshiaki Tounoue, Xiaoqing Wen, Seiji Kajihara (K I T), Kohei Miyase (JST), Tatsuya Suzuki, Yuta Yamato (K I T) 		High Power dissipation when the response to a test vector is captured by flip-flops in scan testing which may cause exce... [more] CPM2006-148 ICD2006-190
pp.109-114
 Results 21 - 26 of 26 [Previous]  /   
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